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Datasheet File OCR Text:

Dual 6-Phase + 1-Phase PWM Controller for VR12/IMVP7 Applications
ISL6366
The ISL6366 is a dual PWM controller; its 6-phase PWMs control the microprocessor core or memory voltage regulator, while its single-phase PWM controls the peripheral voltage regulator for graphics, system agent, or processor I/O. The ISL6366 utilizes Intersil's proprietary Enhanced Active Pulse Positioning (EAPP) modulation scheme to achieve the extremely fast transient response with fewer output capacitors. The ISL6366 is designed to be compliant to Intel VR12/IMVP7 specifications. It accurately monitors the load current via the IMON pin and reports this information via the IOUT register to the microprocessor, which sends a PSI# signal to the controller at low power mode via SVID bus. The controller enters 1- or 2-phase operation in low power mode (PSI1); in the ultra low power mode (PSI2,3), it can further drop the number of phases and enable the diode emulation of the operational phase. In low power modes, the magnetic core and switching losses are significantly reduced, yielding high efficiency at light load. After the PSI# signal is de-asserted, the dropped phase(s) are added back to sustain heavy load transient response and efficiency. Today's microprocessors require a tightly regulated output voltage position versus load current (droop). The ISL6366 senses the output current continuously by measuring the voltage across the dedicated current sense resistor or the DCR of the output inductor. The sensed current flows out of the FB pin to develop the precision voltage drop across the feedback resistor for droop control. Current sensing circuits also provide the needed signals for channel-current balancing, average overcurrent protection and individual phase current limiting. The TM and TMS pins are to sense an NTC thermistor's temperature, which is internally digitized for thermal monitoring and for integrated thermal compensation of the current sense elements of the respective regulator. The ISL6366 features remote voltage sensing and completely eliminates any potential difference between remote and local grounds. This improves regulation and protection accuracy. The threshold-sensitive enable input is available to accurately coordinate the start-up of the ISL6366 with other voltage rails.
Features
* Intel VR12/IMVP7 Compliant - SerialVID with Programmable IMAX, TMAX, BOOT, ADDRESS OFFSET Registers * Intersil's Proprietary Enhanced Active Pulse Positioning (EAPP) Modulation Scheme, Patented - Voltage Feed-forward and Ramp Adjustable Options - High Frequency and PSI Compensation Options - Variable Frequency Control During Load Transients to Reduce Beat Frequency Oscillation - Linear Control with Evenly Distributed PWM Pulses for Better Phase Current Balance During Load Transients * Dual Outputs - Output 1 (VR0): 1 to 6-Phase, Coupled Inductor Compatibility, for Core or Memory - Output 2 (VR1): Single Phase for Graphics, System Agent, or Processor I/O - Differential Remote Voltage Sensing - 0.5% Closed-loop System Accuracy Over Load, Line and Temperature - Phase Doubler Compatibility (NOT Phase Dropping) * Proprietary Active Phase Adding and Dropping with Diode Emulation Scheme For Enhanced Light Load Efficiency * Programmable Slew Rate of Fast Dynamic VID with Dynamic VID Compensation (DVC) for VR0 * Dynamic VID Compensation (DVS) for VR1 at No Droop * Droop and Diode Emulation Options * Programmable 1 or 2-Phase Operation in PSI1/2/3 Mode * Programmable Standard or Coupled-Inductor Operation * Precision Resistor or DCR Differential Current Sensing - Integrated Programmable Current Sense Resistors - Integrated Thermal Compensation - Accurate Load-Line (Droop) Programming - Accurate Channel-Current Balancing - Accurate Current Monitoring * Average Overcurrent Protection and Channel Current Limit With Internal Current Comparators * Precision Overcurrent Protection on IMON & IMONS Pins * Independent Oscillators, up to 1MHz Per Phase, for Cost, Efficiency, and Performance Optimization * Dual Thermal Monitoring and Thermal Compensation * Start-up Into Pre-Charged Load * Pb-Free (RoHS Compliant)
January 3, 2011 FN6964.0
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
ISL6366 Ordering Information
PART NUMBER (Note 1, 2, 3) ISL6366CRZ ISL6366IRZ NOTES: 1. Add "-T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6366. For more information on MSL please see techbrief TB363. PART MARKING ISL6366 CRZ ISL6366 IRZ TEMP. RANGE (C) 0 to +70 -40 to +85 PACKAGE (Pb-Free) 60 Ld 7x7 QFN 60 Ld 7x7 QFN PKG. DWG. # L60.7x7 L60.7x7
Pin Configuration
ISL6366 (60 LD 7X7 QFN) TOP VIEW
EN_VTT ISEN6+ ISEN3+ ISEN1+ ISEN4+ ISEN2+ ISEN5+ ISEN6ISEN3ISEN1ISEN4ISEN2ISEN5PWM6 PWM3 45 PWM1 44 PWM4 43 PWM2 42 PWM5 41 VCC 40 FS_DRP 39 RSET GND 38 SICI 37 TM 36 BTS_DES_TCOMPS 35 BT_FDVID_TCOMP 34 NPSI_DE_IMAX 33 ADDR_IMAXS_TMAX 32 PWMS 31 ISENS16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 HFCOMPS/DVCS VR_HOT# NC2 VR_RDY COMPS FSS_DRPS TMS NC1 NC3 VR_RDYS VSENS IMONS FBS RGNDS ISENS+
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 NC4 1 NC5 2 EN_PWR 3 RAMP_ADJ 4 RGND 5 VSEN 6 HFCOMP 7 PSICOMP 8 FB 9 COMP 10 DVC 11 IMON 12 SVDATA 13 SVALERT# 14 SVCLK 15
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FN6964.0 January 3, 2011
ISL6366 Driver Recommendation
DRIVER ISL6627 ISL6620 ISL6620A QUIESCENT CURRENT (mA) 1.0 1.2 GATE DRIVE VOLTAGE 5V 5V # OF DRIVERS Single Single DIODE EMULATION (DE) Yes Yes GATE DRIVE DROP (GVOT) No No COMMENTS For PSI# channel and its coupled channel in coupled inductor applications or all channels For PSI# channel and its coupled channel in coupled inductor applications or all channels. Shorter body diode conduction time when enters PSI2 mode at a fixed voltage. For dropped phases or all channels without DE For dropped phases or all channels without DE Phase Doubler with Integrated Drivers, up to 12Phase. For all channels with DE Disabled PWM Doubler for DrMOS, up to 12 or 24-Phase. For all channels with DE Disabled For PSI# channel and its coupled channel in coupled inductor applications or all channels For PSI# channel and its coupled channel in coupled inductor applications or all channels. Shorter body diode conduction time when enters PSI2 mode at a fixed voltage. For PSI# channel and its coupled channel in coupled inductor applications or all channels. Shorter body diode conduction time when enters PSI2 mode at a fixed voltage. For dropped phases or all channels without DE
ISL6596 ISL6610 ISL6610A ISL6611A ISL6617 ISL6625 ISL6622
0.19 0.24 1.25 5.0 1.2 5.5
5V 5V 5V N/A 12V 12V
Single Dual Dual N/A Single Single
No No No No Yes Yes
No No No No Yes Yes
ISL6622A ISL6622B
5.5
12V
Single
Yes
No
ISL6625A
1.0
12V
Single
No
No
NOTE: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow for dual footprint layout implementation to optimize MOSFET selection and efficiency. 5V Drivers are more suitable for high frequency and high efficiency applications.
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FN6964.0 January 3, 2011
ISL6366 ISL6366 Internal Block Diagram
FSS_DRPS ISL6366A & ISL6367 ONLY; ISL6366 = NC4-5 INPUT CURRENT MONITOR THERMAL MONITOR VR_RDYS PWMS TCOMPS VR1: CLOCK AND RAMP GENERATOR THGS TEMPERATURE COMPENSATION AVERAGE & PEAK CURRENT LIMIT IDROOPS EAPP MODULATOR 1.15V FS_DRP RAMP_ADJ DAC & OFFSET VR0: CLOCK AND RAMP GENERATOR TMAX VR1 REGs SVID BUS INTERFACE VR0 REGs LATCH POWER-ON RESET (POR) + N RESET + 0.85V EN_PWR_CFP CFP FOR ISL6367 & ISL6366A 0.85V EN_VTT VCC OCP + IMONS 1.11V E/A ISENS+ SHED 1.11V + OCP CHANNEL CURRENT BALANCE AND PEAK CURRENT LIMIT + CHANNEL DETECT N ISEN1+ ISEN1ISEN2+ I_TRIP 1.15V GND TMAX VR_HOT# TM TCOMP TEMPERATURE COMPENSATION GAIN ADJUST TEMPERATURE COMPENSATION 1 N ISEN2ISEN3+ CHANNEL CURRENT SENSE ISEN3ISEN4+ ISEN4ISEN5+ THERMAL MONITOR THG ISEN5ISEN6+ ISEN6RSET SOFT-START AND FAULT LOGIC SOFT-START AND FAULT LOGIC EAPP MODULATOR DAC & OFFSET + OVP 175mV + E/A EAPP MODULATOR PWM2 EAPP MODULATOR PSI# HFCOMP COMP "SICI" FOR ISL6366: "IAUTO" FOR ISL6366A & ISL6367 SICI AUTO PHASE SHEDDING SHED IDROOP EAPP MODULATOR OCP ISENIN+ ISENINTMS VSENS HFCOMPS/DVCS HIGH FREQUENCY COMPENSATION IDROOPS FBS RGNDS COMPS VR_RDY BTS_DES_TCOMPS BT_FDVID_TCOMP NPSI_DE_IMAX ADDR_IMAXS_TMAX SVCLK SVALERT# SVDATA TCOMP ISL6367 I2CLK ONLY; ISL6366 & PMALERT# ISL6366A I2DATA = NC1-3 PSI# + + IIN OCP + ISENS+
I_TRIP
THGS + OVP 175mV + E/A -
+
TCOMPS
I2C /PMBUS INTERFACE
PWM1
THGS THG IIN VSEN RGND DVC FB PSICOMP X4/3
+ + + REF
PWM5
HIGH FREQUENCY COMPENSATION
PWM6
IMON
4
IDROOP
FN6964.0 January 3, 2011
ISL6366 Typical Application: 6-Phase Standard-Inductor VR and 1-Phase VR
+5V VINF +5V BOOT UGATE VCC ISL6627 DRIVER DVC FB PSICOMP HFCOMP VSEN VTT SVDATA SVALERT# SVCLK VR_RDY VR_RDYS VR_HOT# PWM3-5 VINF ISL6366 ISEN3-5ISEN2-5+ VINF VINF CFP RAMP_ADJ PWM6 IMON IMONS FS_DRP FSS_DRPS +5V +5V +5V BTS_DES_TCOMPS BT_FDVID_TCOMP +5V ADDR_IMAXS_TMAX PWMS +5V NPSI_DE_IMAX ISENSPWM GND ISEN6ISEN6+ USED WITH ISL6366A/67 RISENIN2 RISENIN1 VIN RSENIN VINF PWM EN_PWR +5V BOOT UGATE VCC ISL6596 DRIVER PHASE GND LGATE CPU LOAD PWM2 ISEN2ISEN2+ PWM RGND EN_VTT COMP VCC PWM1 ISEN1ISEN1+ +5V BOOT UGATE VCC ISL6627 DRIVER PHASE GND LGATE VINF PWM PHASE GND LGATE
ISENINISENIN+
+5V
BOOT UGATE VCC ISL6627 DRIVER PHASE GND LGATE GPU LOAD
ISENS+ +5V NTC TM SICI RSET TMS RGNDS VSENS NTC HFCOMPS/DVCS COMPS FBS
NTC: BETA = 3477
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FN6964.0 January 3, 2011
ISL6366 Typical Application: 6-Phase Coupled-Inductor VR and 1-Phase VR
+5V VIN +5V BOOT UGATE VCC ISL6627 DRIVER PHASE GND LGATE
DVC FB PSICOMP HFCOMP VSEN VTT SVDATA SVALERT# SVCLK VR_RDY VR_RDYS VR_HOT# OVP RGND EN_VTT
COMP
VCC PWM1 ISEN1ISEN1+ +5V
PWM
VIN BOOT UGATE VCC ISL6627 DRIVER PHASE GND LGATE
PWM4 ISEN4ISEN4+
PWM
PWM2/5 ISL6366 ISEN2/5ISEN2/5+
VIN VIN EN_PWR RAMP_ADJ PWM3/6 ISEN3/6ISEN3/6+ CPU LOAD
IMON IMONS FS_DRP FSS_DRPS +5V +5V +5V BTS_DES_TCOMPS BT_FDVID_TCOMP +5V ADDR_IMAXS_TMAX PWMS +5V NPSI_DE_IMAX ISENSPWM GND
VIN
+5V
BOOT UGATE VCC ISL6627 DRIVER PHASE GND LGATE GPU LOAD
ISENS+ +5V NTC TM SICI RSET +5V NTC: BETA = 3477 TMS RGNDS VSENS NTC HFCOMPS/DVCS COMPS FBS
NTC1 NETWORK IS NOT NEEDED IF TMS IS USED FOR VR1, GPU
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FN6964.0 January 3, 2011
ISL6366 Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PWM Modulation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PWM and PSI# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Diode Emulation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Channel-Current Balance for VR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Load-Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output-Voltage Offset Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Dynamic VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operation Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Current Sense Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VR_Ready Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Thermal Monitoring (VR_HOT#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Integrated Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Hard-wired Registers (Patent Pending). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Dynamic VID Compensation (DVC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Disabling Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SVID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 General Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Current Sensing Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Load-Line Regulation Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Output Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Switching Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Layout and Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Pin Noise Sensitivity, Design and Layout Consideration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Powering Up And Open-Loop Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Voltage-Regulator (VR) Design Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Absolute Maximum Ratings
VCC, VR_RDY, VR_RDYS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V NC4, NC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V to 27V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V to VCC + 0.3V
Thermal Information
Thermal Resistance (Notes 4, 5) JA (C/W) JC (C/W) 60 Ld 7x7 QFN Package . . . . . . . . . . . . . . . 24 1.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V 5% Ambient Temperature ISL6366CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C ISL6366IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, VCC = 5V, Unless Otherwise specified. Boldface limits apply over the
operating temperature range. PARAMETER TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS
VOLTAGE REGULATOR (VR) ADDRESS
Multiple-Phase Voltage Regulator (VR0) ADDRESS Hexadecimal Format Single-Phase Voltage Regulator (VR1) ADDRESS Hexadecimal Format 0 1 EVN ODD C 7 -
VCC SUPPLY CURRENT
Nominal Supply Shutdown Supply VCC = 5VDC; EN_PWR = 5VDC; RT = 125k, ISEN1-6 = 0A VCC = 5VDC; EN_PWR = 0VDC; RT = 125k 23 16.5 28 22 34.5 28.5 mA mA
POWER-ON RESET AND ENABLE
VCC Rising POR Threshold VCC Falling POR Threshold EN_PWR_FT Rising Threshold EN_PWR_FT Falling Threshold EN_VTT Rising Threshold EN_VTT Falling Threshold 4.30 3.75 0.830 0.730 0.830 0.730 4.40 3.90 0.850 0.750 0.850 0.750 4.50 4.0 0.870 0.770 0.870 0.770 V V V V V V
DAC (VID+OFFSET)
System Accuracy of ISL6366CRZ (DAC = 1V to 2.155 V, TJ = 0C to +70C) System Accuracy of ISL6366CRZ (DAC = 0.8V to 1V, TJ = 0C to +70C) System Accuracy of ISL6366CRZ (DAC = 0.25V to 0.8V, TJ = 0C to +70C) System Accuracy of ISL6366IRZ (DAC = 1V to 2.155V, TJ = -40C to +85C) System Accuracy of ISL6366IRZ (DAC = 0.8V to 1V, TJ = -40C to +85C) System Accuracy of ISL6366IRZ (DAC = 0.25V to 0.8V, TJ = -40C to +85C) (Note 6, Closed-Loop) (Note 6, Closed-Loop) (Note 6, Closed-Loop) (Note 6, Closed-Loop) (Note 6, Closed-Loop) (Note 6, Closed-Loop) -0.5 -5 -8 -0.6 -6 -9 0.5 5 8 0.6 6 9 %VID mV mV %VID mV mV
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Electrical Specifications Recommended Operating Conditions, VCC = 5V, Unless Otherwise specified. Boldface limits apply over the
operating temperature range. (Continued) PARAMETER TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS
OSCILLATORS
Accuracy of VR0 Switching Frequency Setting Accuracy of VR1 Switching Frequency Setting Maximum Switching Frequency Minimum Switching Frequency Soft-start Ramp Rate for VR0 Soft-start Ramp Rate for VR1 Maximum Duty Cycle Per PWM for VR0 Maximum Duty Cycle for VR1 400kHz, VRAMP < 1.8V 400kHz FDVID = 10mV/s FDVID = 20mV/s RFS = 125k RFSS = 125k 360 360 1.0 2.5 5.0 2.5 95 69 400 400 2.8 5.55 2.8 97 83 440 440 0.08 3.2 6.2 3.2 99 96 kHz kHz MHz MHz mV/s mV/s mV/s % %
PWM GENERATOR (Note 7)
Sawtooth Amplitude for VR0 Sawtooth Amplitude for VR0 Sawtooth Amplitude for VR0 Maximum Adjustable Ramp for VR0 Minimum Adjustable Ramp for VR0 Sawtooth Amplitude for VR1 RRAMP_ADJ = Open, all Switching Frequency RRAMP_ADJ = 2.4M to 12V, 500kHz RRAMP_ADJ = 1.2M to 12V, 500kHz Applicable to VR0 Only Applicable to VR0 Only Applicable to VR1 Only 1 0.5 1 3 0.3 2.0 V V V V V V
ERROR AMPLIFIER
Open-Loop Gain Open-Loop Bandwidth Slew Rate Maximum Output Voltage Output High Voltage Output Low Voltage No Load 2mA Load 2mA Load RL = 10k to ground 4.1 3.8 0.85 96 80 25 4.4 4.1 0.96 4.6 4.6 1.2 dB MHz V/s V V V
PWM OUTPUT (PWM[6:1] and PWMS)
Sink Impedance Source Impedance PWM PSI2/3/Decay Mid-Level PWM = Low with 1mA Load PWM = High, Forced to 3.7V 0.4mA Load 38 170 150 40 44 %VCC
CURRENT SENSE AND OVERCURRENT PROTECTION
Sensed Current Tolerance of VR0 ISEN1-6 = 40A; CS Offset and Mirror Error Included, RSET = 12.8k ISEN1-6 = 80A; CS Offset and Mirror Error Included, RSET = 12.8k Sensed Current Tolerance of VR1 ISENS = 40A; RISENS = 100 ISENS = 80A; RISENS= 100 VR0 Average Overcurrent Trip Level at Normal CCM PWM Mode VR0 Average Overcurrent Trip Level at PSI1/2/3 Mode CS Offset and Mirror Error Included, RSET = 12.8k N = 6 Drop to 1-Phase 36.5 75.5 33 69.5 40.6 80.3 37 75 100 99 100 44 85.5 41 81 A A A A A A A
VR0 Average Overcurrent Trip Level at PSI1 Mode N = 6 Drop to 2-Phase
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Electrical Specifications Recommended Operating Conditions, VCC = 5V, Unless Otherwise specified. Boldface limits apply over the
operating temperature range. (Continued) PARAMETER VR0 Peak Current Limit for Individual Channel VR1 Average Overcurrent Trip Level IMON, IMOS Clamped and OCP Trip Level IMON, IMONS VOLTAGE IMAX (FF) TRIP POINT Higher than this will be "FF" CS Offset and Mirror Error Included, RISENS = 100 TEST CONDITIONS MIN (Note 7) 1.085 875 TYP 139 100 1.12 880 MAX (Note 7) UNITS 1.14 887 A A V mV
THERMAL MONITORING
VR_HOT# Pull-down Impedance TM Voltage at Thermal Trip (Programmable via TMAX) VR_HOT# and Thermal Alert# Hysteresis Leakage Current of VR_HOT# With external pull-up resistor connected to VCC TMAX = +100C, see Table 7 8.4 9.2 39.12 3 13 1 %VCC C A
VR READY AND PROTECTION MONITORS
Leakage Current of VR_RDY, VR_RDYS VR READY Low Voltage Overvoltage Protection Threshold With pull-up resistor externally connected to VCC 4mA Load Prior to the End of Soft-start After the End of Soft-start, the voltage above VID Overvoltage Protection Reset Hysteresis 160 98 2.30 179 107 1 0.3 200 117 A V V mV mV
SVID BUS
ALERT# Pull-down Impedance SVDATA SVCLK Maximum Speed SVCLK Minimum Speed NOTES: 6. These parts are designed and adjusted for accuracy with all errors in the voltage loop included. 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 11 11 26.5 13.0 13 13 MHz MHz
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ISL6366 Functional Pin Descriptions
Note: VR0 is the multi-phase voltage regulator. VR1 is the single-phase voltage regulator. Refer to Table 13 on page 35 and Table 14 on page 39 for Design and Layout Consideration. VCC - Supplies the power necessary to operate the chip. The controller starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin directly to a +5V supply with a high quality ceramic capacitor. GND - The bottom metal base of ISL6366 is the GND. Bias and reference ground for the IC. It is also the return for all PWM output drivers. EN_PWR - This pin is a threshold-sensitive enable input. Connecting the power train input supply to this through an appropriate resistor divider provides a means to synchronize the power sequencing of the controller and the MOSFET driver ICs. When EN_PWR is driven above 0.85V, the ISL6366 is actively depending on status of the EN_VTT, the internal POR, and pending fault states. Driving EN_PWR below 0.75V will clear all fault states and prepare the ISL6366 to soft-start when reenabled. EN_VTT - This pin is a threshold-sensitive enable input. It's typically connected to the output of the VTT voltage regulator in the computer mother board. When this pin is driven above 0.85V, the ISL6366 is actively depending on status of the EN_PWR, the internal POR, and pending fault states. Driving this below 0.75V will clear all fault states and prepare the ISL6366 to soft-start when re-enabled. VSEN - This pin monitors the regulator VR0 output for overvoltage protection. Connect this pin to the positive rail remote sensing point of the microprocessor or load. This pin tracks with the FB pin. If a resistive divider is placed on the FB pin, a resistive divider with the same ratio should be on the VSEN pin. Tie it to GND if not used. RGND - This pin compensates the offset between the remote ground of the VR0 load and the local ground of this device. Connect this pin to the negative rail remote sensing point of the microprocessor or load. Tie it to GND if not used. COMP and FB - COMP and FB are the output and inverting input of the precision error amplifier, respectively. A type III loop compensation network should be connected to these pins, while the FB's R-C network should connect to the positive rail remote sensing point of the microprocessor or load. Combined with RGND, the potential difference between remote and local rails is completely compensated and it improves regulation accuracy. A properly chosen resistor between FB and remote sensing point can set the load line (droop, if enabled), because the sensed current will flow out of FB pin. The droop scale factor is set by the ratio of the effective ISEN resistors (set by RSET) and the inductor DCR or the dedicated current sense resistor. COMP is tied back to FB through an external R-C network to compensate the regulator. An RC from the FB pin to ground will be needed if the output is lagging from the DAC, typically for applications with too many output capacitors and droop enabled. VR_RDY - VR_RDY indicates that soft-start has completed and this VR0 output remains in normal operation. It is an open-drain 11 logic output. When OCP or OVP occurs in VR0, VR_RDY will be pulled to low. TM - TM is an input pin for the VR0 temperature measurement. Connect this pin through an NTC thermistor to GND and a resistor to VCC of the controller. The voltage at this pin is inversely proportional to the VR temperature. The device monitors the VR temperature based on the voltage at the TM pin. Combining with "TCOMP" setting, VR0's sensed current is thermally compensated. The VR_HOT# asserts low if the sensed temperature at this pin is higher than the maximum desired temperature, "TMAX". The NTC should be placed close to the current sensing element, the output inductor or dedicated sense resistor on Phase 1 of VR0. A decoupling capacitor (0.1F) is typically needed to be in close proximity to the controller. If not used, connect this pin to TMS or 1M/2M resistor divider, but DON'T tie it to VCC or GND. VR_HOT# - VR_HOT# is used as an indication of high VR temperature. It is an open-drain logic output. It will be open if the measured VR temperature is less than a certain level, and pulled low when the measured VR temperature reaches a certain level. PWM[6:1] - Pulse width modulation outputs of VR0. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM[6:2]. Tie PWM(N+1) to VCC to configure for N-phase operation. PWM firing order is sequential from 1 to N with N being the number of active phases. If PWM1 is tied high, the respective address is released for use, i.e, the VR0 is disabled and does not respond to the SVID commands. IMON, VSEN, FB, ISEN[6:1]-, and RGND must be grounded to remove OCP and OVP faults of VR0, while TM can be tied to TMS, or 1/2 ratio resistor divider. In addition, must connect FS_DRP to 1M from GND or VCC. See Table 1 on page 15 and Table 13 on page 35 for details. PWMS - Pulse width modulation output of VR1. Connect this pin to the PWM input pin of the Intersil driver IC. Tie this pin to VCC to disable this PWM channel, while the respective address is released for use, i.e., the VR1 is disabled and does not respond to the SVID commands. IMONS, VSENS, FBS, ISENS-, and RGNDS must be grounded to remove OCP and OVP faults of VR1, while TMS can be tied to TM, or 1/2 ratio resistor divider. In addition, must connect FSS_DRPS to 1M from GND or VCC for proper SVID address. See Table 13 on page 35 for details. ISEN[6:1]+, ISEN[6:1] - The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers of VR0. The sensed current is used for channel current balancing, overcurrent protection, and droop regulation. Inactive channels should have their respective current sense inputs, ISEN[6:#]- grounded, and ISEN[6:#]+ open. For example, ground ISEN[6:5]- and open ISEN[6:5]+ for 4-phase operation. DON'T ground ISEN[6:1]+. For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor (typically output rail). The voltage across the sense capacitor is proportional to the inductor current. Therefore, the sensed current is proportional to the inductor current and scaled by the DCR of the inductor and RSET. When VR0 is disabled, have ISEN[6:1]- grounded and ISEN[6:1]+ open. RSET - A resistor connected from this pin to ground sets the current gain of the current sensing amplifier for VR0. The RSET resistor value can be from 3.84k to 115.2k and is 64x of the required RISEN resistor value. Therefore, the current sense gain
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resistor value can be effectively set at 60 to 1.8k. When VR0 is disabled (PWM1 = VCC), connect 1M from this pin to GND. ISENS+, ISENS - The ISENS+ and ISENS- pins are current sense inputs to the differential amplifier of VR1. The sensed current is used for overcurrent protection and droop regulation. For DCR sensing, connect each ISENS- pin to the node between the RC sense elements. Tie the ISENS+ pin to the other end of the sense capacitor through a resistor, RISENS. The voltage across the sense capacitor is proportional to the inductor current. Therefore, the sense current is proportional to the inductor current and scaled by the DCR of the inductor and RISENS. When VR1 is disabled, have ISENS- grounded and ISENS+ open. IMON - IMON is the output pin of sensed, thermally compensated (if internal thermal compensation is used) average current of VR0. The voltage at the IMON pin is proportional to the load current and the resistor value, and internally clamped to 1.12V. If the clamped voltage is triggered, it will initiate an overcurrent shutdown. By choosing the proper value for the resistor at IMON pin, the overcurrent trip level can be set to be lower than the fixed internal overcurrent threshold. During the dynamic VID, the OCP function of this pin is disabled to avoid false triggering. Tie it to GND if not used. Does not need to refer to the remote ground for VR12/IMPV7 applications. FS_DRP - A resistor placed from this pin to GND/VCC will set the switching frequency of VR0. The relationship between the value of the resistor and the switching frequency will be approximated by Equation 4 on page 16. This pin is also used to set the droop option. The droop is disabled when the resistor is pulled to VCC and enabled when the resistor is pulled to ground. When VR0 is disabled (PWM1 = VCC), connect 1M from this pin to GND. HFCOMP - Connect a resistor with a similar value of the feedback impedance to the VR0 output to compensate the level-shifted output voltage during high-frequency load transient events. Connecting more than 2x of feedback impedance to this pin or keeping it open virtually disables this feature. PSICOMP - Connect an RC to the type III compensation capacitor of the VR0 output voltage. This improves loop gain and load transient response in PSI1/2/3/Decay mode. An open pin will disable this feature. SICI - When this pin is pulled to ground, it sets for standard inductor (SI) operation; when this pin is pulled to VCC, it sets coupled-inductor (CI) operation. The phase dropping operation options for PSI1/2/3 mode are summarized in Table 3 on page 16. DVC - A series resistor and capacitor can be connected from this pin to the FB pin to compensate and smooth dynamic VID transitions. VSENS, RGNDS, FBS, COMPS, VR_RDYS, IMONS, FSS_DRPS, HFCOMPS - These pins are for VR1 regulator and have the same function as VSEN, RGND, FB, COMP, VR_RDY, IMON, FS_DRP, and HFCOMP, respectively. However, HFCOMPS has multiplexed the DVCS function, while the FSS_DRPS does have additional programming feature as described in the following. HFCOMPS/DVCS - Connect a resistor with a similar value of the feedback impedance to the VR1 output to compensate the levelshifted output voltage during high-frequency load transient events. Connecting more than 2x of feedback impedance to this 12 pin or keeping it open virtually disables this feature. If the droop option of VR1 is disabled, then this pin becomes DVCS. A series resistor and capacitor can be connected from this pin to the FBS pin to compensate and smooth dynamic VID transitions for VR1 output. FSS_DRPS - A resistor placed from this pin to ground/VCC will set the switching frequency of VR1. The relationship between the value of the resistor and the switching frequency will be approximated by Equation 4 on page 16. This pin is also used to set the droop option. The droop is disabled when the resistor is pulled to VCC and enabled when the resistor is pulled to ground. When VR1 is disabled (PWMS = VCC), connect 1M from this pin to GND for ADDR: 0, 2, 4, and 6; to VCC for ADDR: 8, A, and C. TMS - This is an input pin for the temperature monitoring. Connect this pin through an NTC thermistor to GND and a resistor to VCC of the controller. The voltage at this pin is inversely proportional to the VR temperature. The thermal information can be used for VR1 thermal compensation. If TCOMPS is set at "OFF" bit, the integrated thermal compensation is disabled; otherwise, the thermal information is used for VR1 thermal compensation with "TCOMPS" data. Combined with TM pin, the thermal information at TMS pin will also be used to trigger VR_HOT#. The NTC should be placed close to the current sensing element, the output inductor or dedicated sense resistor of VR1. If not used, connect this pin to TM or 1M/2M resistor divider, but DON'T tie it to VCC or GND. SVCLK - An input pin for a synchronous clock signal of SerialVID bus from CPU. SVDATA - An input pin for transferring open-drain data signals between CPU and VR controller. SVALERT# - An output pin for transferring the active low signal driven asynchronously from the VR controller to CPU. RAMP_ADJ - An input pin to set the slope of Sawtooth for VR0. The slope of the Sawtooth is proportional to the current, sampled by the an active pull-down device, into this pin. When the resistor is connected to the input voltage of the VR0, the slope will be proportional to the input voltage, achieving voltage feed-forward compensation. For a 12V supply (VIN) and 2.4M pull up (~ 5A), it sets a nominal 0.25V/s up-ramp slope at 500kHz switching frequency, corresponding to 0.5V peak-to-peak up ramp. The maximum peak-to-peak up ramp should be limited to 3V, corresponding a pull-down current of 30A at 500kHz, i.e., the pull-up impedance should be higher than VIN/30A at 500kHz. See Equation 3 for the up ramp amplitude calculation. When this pin is floating, the up ramp amplitude sets to 1V regardless of the switching frequency and the feedforward function is disabled. ADDR_IMAXS_TMAX, BTS_DES_TCOMPS, BT_FDVID_TCOMP, NSPI_DE_IMAX - These are four register pins to program system parameters. The meaning of each is described as below. See Table 9 for the summary. ADDR_IMAXS_TMAX (0C): ADDR - An input pin to set the address offset register of VR0 (0, 2, 4, 6, 8, A, C) and VR1 (1, 3, 5, 7). E/F is an ALL call address and is not used.
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ISL6366
IMAXS - An input pin to set the maximum current, ICCMAX, register of the VR1. It can be programed to 20A, 25A, 30A, and 35A when the droop is enabled (RFSS_DRPS = GND). This register represents the maximum allowed load current for VR1 and corresponds to a 900mV (typically set) at IMONS. When VR1 droop is disabled (RFSS_DRPS = VCC), the ICCMAX can be programed to15A, 20A, 25A, and 30A. TMAX - An input pin to set the maximum temperature register (TMAX) of the VR0 and VR1 and the thermal trip point of VR_HOT#. It covers +90C to +120C with 5C/step. The register represents the maximum allowed temperature of VR0 and VR1, and programs the over-temperature trip point at VR_HOT#. The typical application should use +100C or lower since the NTC thermistor temperature represents the PCB, not the hottest component on the board. In addition, the NTC thermistor typically picks up a temperature lower than the PCB due to the thermal impedance between PCB and NTC. BTS_DES_TCOMPS (0D): BTS - An input pin to set the start-up boot voltage register of VR1. It has four levels: 0, 0.9V, 1.0, and 1.1V for graphic rails with droop enabled (RFSS_DRPS = GND). When the droop is disabled (RFSS_DRPS = VCC), the boot levels will be changed to 0, 0.85V, 0.925V, 1.05V for VCCIO and System Agent rails. DES - An input pin to set the diode emulation (DE) operation register of VR1 at PSI2, PSI3, and Decay modes. At PSI1 mode, the VR1 always operates in CCM mode. When the diode emulation is disabled, the output will decay at the rate of setVID Slow; however, the SVID bus is still be acknowledged of execution of the command. TCOMPS - An input pin to set the mis-matching temperature (+13C to +43C) between the actual sensed inductor and the NTC thermistor at TMS pin. The voltage sensed on the TMS pin is utilized as the temperature input to adjust the droop current and the overcurrent protection limit to effectively compensate for the temperature coefficient of the current sense element of VR1. To implement the integrated temperature compensation, select a proper temperature offset "TCOMP," other than the "OFF" value, which is to disable the integrated temperature compensation function. When the VR1 channel's droop is disabled by pulling FSS_DRPS pin high with a frequency set resistor, TCOMPS register will be used to set the address of PMBus, 80-8Eh for VR0 and E0EEh for VR1 in ISL6367. BT_FDVID_TCOMP (0E): BT - An input pin to set the start-up boot voltage register of VR0. It has four levels: 0V, 0.9V, 1.0V, and 1.1V for core applications. When the droop is disabled, the boot levels will be changed to 0V, 1.2V, 1.35V, and 1.5V for memory applications. FDVID - An input pin to set the slew rate of fast Dynamic VID. It has choices of 10mV/s and 20mV/s. This will only apply to VR0, not VR1. TCOMP - An input to set the mis-matching temperature (+13C to +43C) between the actual sensed inductor of VR0 regulator and the NTC thermistor at the TM pin. The voltage sensed on the TM pin is utilized as the temperature input to adjust the droop current and the overcurrent protection limit to effectively compensate for the temperature coefficient of the current sense element of VR0. To implement the integrated temperature compensation, select a proper temperature offset "TCOMP," other than the "OFF" value, which is to disable the integrated temperature compensation function. NSPI_DE_IMAX (0F): NPSI - An input pin to set the number of phases dropping at low power mode. See Table 3 on page 16 for more details. DE - An input pin to set the diode emulation (DE) operation register of VR0 at PSI2, PSI3, and Decay modes. At PSI1 mode, the VR0 always operates in CCM mode. When the diode emulation is disabled, the output will decay at the rate of setVID Slow; however, the SVID bus is still be acknowledged of execution of the command. IMAX - An input pin to set the maximum current, ICCMAX, register of the VR0 voltage regulator. It has a range of 15A to 165A with 5A/step. In 5- and 6-Phase operation, it will add 90A offset over the previous range and cover the range of 105A to 255A with 5A/step. This register represents the maximum allowed load current for VR0 and corresponds to a 900mV (typically set) at IMON. NC[1:3] - No connection pins for ISL6366 and ISL6366A. Reserved for PMBus [I2DATA, PMALERT#, I2CLK] in ISL6367. NC[4:5] - No connection pins for ISL6366. Reserved for input current sensing [ISENIN-, ISENIN+] in ISL6366A and ISL6367.
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ISL6366 Operation
The ISL6366 is a dual PWM controller; its 6-phase PWMs control microprocessor core or memory voltage regulator, while its singlephase PWM controls the peripheral voltage regulator such graphics rail, system agent, or processor I/O. The ISL6366 is designed to be compliant to Intel VR12/IMVP7 specifications with SerialVID Features. The system parameters and SVID required registers are programmable with four dedicated pins. It greatly simplifies the system design for various platforms and lowers inventory complexity and cost by using a single device. In addition, this controller is compatible, except for forced dropping via PWM lines, with phase doublers (ISL6611A and ISL6617), which can double or quadruple the phase count. For instance, the multi-phase PWM can realize a beyond 6-phase and up to 24-phase count system, and the single-phase PWM can be scaled up to 2 or 4 phases. The higher phase count system can improve thermal distribution and power conversion efficiency at heavy load.
IL1 + IL2 + IL3, 7A/DIV IL1, 7A/DIV PWM1, 5V/DIV IL2, 7A/DIV PWM2, 5V/DIV IL3, 7A/DIV PWM3, 5V/DIV 1s/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER
Multiphase Power Conversion
Microprocessor load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing a single-phase converter (which are both cost-effective and thermally viable), have forced a change to the cost-saving approach of multiphase. The ISL6366 controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. The typical application circuits diagrams on page 5 and page 6 provide the top level views of multiphase power conversion using the ISL6366 controller.
In the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 1 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 2, the peak-to-peak overall ripple current (IC,PP) decreases with the increase in the number of channels, as shown in Figure 2.
RIPPLE CURRENT MULTIPLIER, KRCM
N=1
2 3 4 5 6 DUTY CYCLE (VOUT/VIN)
Interleaving
The switching of each channel in a multiphase converter is timed to be symmetrically out-of-phase with each of the other channels. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the 3-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase, as illustrated in Figure 1. The three channel currents (IL1, IL2, and IL3) combine to form the AC ripple current and the DC load current. The ripple component has three times the ripple frequency of each individual channel current. Each PWM pulse is terminated 1/3 of a cycle after the PWM pulse of the previous phase. The DC components of the inductor currents combine to feed the load. To understand the reduction of ripple current amplitude in the multiphase circuit, examine Equation 1, which represents an individual channel's peak-to-peak inductor current.
( V IN - V OUT ) V OUT I PP = --------------------------------------------------------L F SW V
IN
FIGURE 2. RIPPLE CURRENT MULTIPLIER VS. DUTY CYCLE
Output voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and the summed inductor ripple current. Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and few or less costly output capacitors for any performance specification.
V OUT I C, PP = ------------------ K RCM L F SW (N D - m + 1) (m - (N D)) K RCM = --------------------------------------------------------------------------ND (EQ. 2)
(EQ. 1)
for
m-1NDm m = ROUNDUP ( N D, 0 )
In Equation 1, VIN and VOUT are the input and output voltages respectively, L is the single-channel inductor value, and FSW is the switching frequency.
Another benefit of interleaving is to reduce input ripple current. Input capacitance is determined in part by the maximum input ripple current. Multiphase topologies can improve overall system cost and size by lowering input ripple current and allowing the
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designer to reduce the cost of input capacitors. The example in Figure 3 illustrates input currents from a three-phase converter combining to reduce the total input ripple current.
INPUT-CAPACITOR CURRENT, 10A/DIV
5 10 10 V IN V RAMP = --------------------------------------------F SW R
RAMP_ADJ
(EQ. 3)
With EAPP control and feedforward function, the ISL6366 can achieve excellent transient performance over wide frequency range of load step, resulting in lower demand on the output capacitors. At DC load conditions, the PWM frequency is constant and set by the external resistor between the FS pin and GND during normal mode (PSI0) and low power mode (PSI1). However, when PSI2 or PSI3 is asserted in ultra low power conditions and if the VR is configured into diode emulation operation, the EAPP reduces the switching frequency as the load decreases. Thus, the VR can enter burst mode at extreme light load conditions and improve power conversion efficiency significantly. Under steady state conditions, the operation of the ISL6366 PWM modulator appears to be that of a conventional trailing edge modulator. Conventional analysis and design methods can therefore be used for steady state and small signal operation. The single-phase PWM has a fix ramp of 2V peak to peak. Its overall modulation gain is proportional to the input line.
CHANNEL 1 INPUT CURRENT 10A/DIV CHANNEL 2 INPUT CURRENT 10A/DIV CHANNEL 3 INPUT CURRENT 10A/DIV 1s/DIV
FIGURE 3. CHANNEL INPUT CURRENTS AND INPUT-CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER
The converter depicted in Figure 3 delivers 36A to a 1.5V load from a 12V input. The RMS input capacitor current is 5.9A. Compare this to a single-phase converter also stepping down 12V to 1.5V at 36A. The single-phase converter has 11.9ARMS input capacitor current. The single-phase converter must use an input capacitor bank with twice the RMS current capacity as the equivalent three-phase converter. Figures 29, 30 and 31, as described in "Input Capacitor Selection" on page 38, can be used to determine the input capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the optimal input capacitor solution. Figure 32 shows the single phase input-capacitor RMS current for comparison.
PWM and PSI# Operation
The timing of each channel is set by the number of active channels. The default channel setting for the ISL6366 is six. The switching cycle is defined as the time between PWM pulse termination signals of each channel. The cycle time of the pulse signal is the inverse of the switching frequency set by the resistor between the FS pin and ground. The PWM signals command the MOSFET driver to turn on/off the channel MOSFETs. The ISL6366 can work in a 0 to 6-Phase configuration. Tie PWM(N+1) to VCC to configure for N-phase operation. PWM firing order is sequential from 1 to N with N being the number of active phases, as summarized in Table 1. For 6-phase operation, the channel firing sequence is 1-2-3-4-5-6, and they are evenly spaced 1/6 of a cycle. Connecting PWM6 to VCC configures 5-phase operation, the channel firing order is 1-2-3-4-5 and the phase spacing is 1/5 of a cycle. If PWM2 is connected to VCC, only Channel 1 operation is selected. If PWM1 is connected to VCC, the multi-phase (VR0) operation is turned off; to ensure proper operation of VR1, the VR0's respective pins should be configured as described in "Disabling Output" on page 35.
TABLE 1. PHASE NUMBER AND PWM FIRING SEQUENCE N 6 5 4 3 2 1 0 PHASE SEQUENCE PSI# = PSI0 1-2-3-4-5-6 1-2-3-4-5 1-2-3-4 1-2-3 1-2 1 OFF PWM# TIED TO VCC PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 ACTIVE PHASE PSI# = PSI1 PWM1/4 PWM1/3 PWM1/3 PWM1/2 PWM1/2 PWM1 OFF
PWM Modulation Scheme
The ISL6366 adopts Intersil's proprietary Enhanced Active Pulse Positioning (EAPP) modulation scheme to improve transient performance. The EAPP is a unique dual-edge PWM modulation scheme with both PWM leading and trailing edges being independently moved to give the best response to transient loads. The EAPP has an inherited function, similar to Intersil's proprietary Adaptive Phase Alignment (APA) technique, to turn on all phases together to further improve the transient response, when there are sufficiently large load step currents. The EAPP is a variable frequency but there is linear control over the transient events such that it can evenly distribute the pulses among all phases to achieve very good current balance and eliminate the beat frequency oscillation over wide frequency range of load transients. To further improve the line and load transient responses, the multi-phase PWM features feedforward function to change the up ramp with the input line to maintain a constant overall loop gain over a wide range input voltage. The up ramp of the internal Sawtooth is defined in Equation 3.
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The CPU can enter four distinct power states as shown in Table 2. The ISL6366 supports all states, but it treats PSI2 and PSI3 the same. In addition, the setDecay mode will automatically enter PSI2 State while decaying the output voltage. However, prior to the end of soft-start (i.e: VR_RDY goes high), the lower power mode (PSI1/2/3/Decay) is NOT enabled.
TABLE 2. POWER STATE COMMAND FROM CPU STATE PSI0 PSI1 PSI2 PSI3 Decay DESCRIPTION High Power Mode, All Phases are running Low Power Mode Very Low Power Mode Ultra Low Power Mode, treated as PSI2 Automatically entering PSI2 and Ramping down the output voltage to a target voltage in Decay Mode
The VR1 output can be disabled by pulling PWMS to VCC while the respective address is released for use with a different VR controller. For proper operation of VR0, the VR1's respective pins should be configured as described in "Disabling Output" on page 35. While the controller is operational (VCC above POR, EN_VTT and EN_PWR are both high, valid VID inputs), it can pull the PWM pins to ~40% of VCC (~2V for 5V VCC bias) during various stages, such as soft-start delay, phase shedding operation, or fault conditions (OC or OV events). The matching driver's internal PWM resistor divider can further raise the PWM potential, but not lower it below the level set by the controller IC. Therefore, the controller's PWM outputs are directly compatible with Intersil drivers that require 5V PWM signal amplitudes. Drivers requiring 3.3V PWM signal amplitudes are generally incompatible.
Diode Emulation Operation
To improve light efficiency, the ISL6366 can enter diode emulation operation in PSI2/3 or Decay mode. Users however should select Intersil VR12/IMVP7 compatible drivers: ISL6627 or ISL6625 for PSI# channel(s). The diode emulation should be disabled if non-compatible power stages or drivers are used.
When the SVID bus sends PSI1/2/3 or Set VID Decay command, it indicates the low power mode operation of the processor. The controller will start phase shedding the next switching pulse. The controller allows to drop the number of active phases according to the logic on Table 3 for high light load efficiency performance. The "NPSI" register and SICI pin are to program the controller in operation of non-coupled (SI), 2-phase coupled, or (N-x)-Phase coupled inductors. Different cases yield different PWM output behaviors on both dropped phase(s) and operational phase(s) as PSI# is asserted and de-asserted. When CPU sends PSI0 command, it will pull the controller back to normal CCM PWM operation to sustain an immediate heavy transient load and high efficiency. Note that "N-x" means N-x phase coupled and x phase(s) are uncoupled. For 2-Phase coupled inductor (CI) operation, both coupled phases should be 180 out of phase. In low power states (PSI1/2/3/Decay), the opposite phase of the operational phase will turn on its Low-side MOSFET to circulate inductor current to minimize conduction loss when Phase 1 is high. When PSI1 is asserted, the VR0 is in single-phase CCM operation with PWM1, or 2-phase CCM operation with PWM1 and 2, 3 or 4, as shown in Table 1. The number of operational phases is configured by "NPSI" register, shown in Table 3. In PSI2/3/Decay State, only single phase is in DCM/CCM operation, which is programmed by the "DE" register; the opposite PWM 2, 3, or 4 (depending upon configured maximum phase number as in Table 1) of the PWM1 however will pull low at PWM1 high in CI applications.
TABLE 3. PHASE DROPPING CONFIGURATION AT PSI1 AND PSI2/3/DECAY SICI 0 0 1 1 NPSI 0 1 0 1 CODE SI1 SI2 CI1 CI2 SI, (N-1)-CI SI, (N-2)-CI 2-Phase CI 2-Phase CI PSI1 Mode 1-Phase 2-Phase 1-Phase 2-Phase PSI2/3 & DECAY 1-Phase 1-Phase 1-Phase 1-Phase
Switching Frequency
Both VR0 and VR1 can independently set switching frequency, which is determined by the selection of the frequency-setting resistor, RT, which is connected from FS or FSS pin to GND or VCC. Equation 4 and Figure 4 are provided to assist in selecting the correct resistor value.
5 10 R T = -------------------F SW
10
(EQ. 4)
where FSW is the switching frequency of each phase. Independent frequency for VR0 and VR1 allows for cost, efficiency, and performance optimization. Proximity between the power trains of the two regulators imposed by the space-constrained layouts can lead to cross-coupling. To minimize the effect of cross-coupling between regulators, select operating frequencies at least 50kHz apart.
FREQUENCY-SETTING RESISTOR VALUE (RT, k)
SWITCHING FREQUENCY (Hz)
NOTE: For 2-Phase CI option, the dropped coupled phase turns on LGATE to circulate current when PWM1 is high.
FIGURE 4. SWITCHING FREQUENCY vs RT
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Current Sensing
The ISL6366 senses current continuously for fast response. The ISL6366 supports inductor DCR sensing, or resistive sensing techniques. The associated channel current sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current, IL. The sense current, ISEN, is proportional to the inductor current. The sensed current is used for current balance, load-line regulation, and overcurrent protection. The internal circuitry, shown in Figures 5-6 and 9-10, represents VR1's channel or one channel of the VR0 output, respectively. For VR0 output, the ISEN circuitry is repeated for each channel, but may not be active depending on the status of the PWM[6:2] pins, as described in "PWM and PSI# Operation" on page 15. The input bias current of the current sensing amplifier is typically 60nA; less than 8.34k input impedance (0.5mV offset) is preferred to minimized the offset error, i.e., a larger C value as needed. The voltage on the capacitor VC, can be shown to be proportional to the channel current IL. See Equation 6.
L s ----------- + 1 ( DCR I ) L DCR V C ( s ) = ---------------------------------------------------------------( s RC + 1 ) (EQ. 6)
If the R-C network components are selected such that the RC time constant matches the inductor time constant (R*C = L/DCR), the voltage across the capacitor VC is equal to the voltage drop across the DCR, i.e., proportional to the channel current. With the internal low-offset current amplifier, the capacitor voltage VC is replicated across the sense resistor RISEN. Therefore, the current out of the ISENS+ pin, ISEN, is proportional to the inductor current. Because of the internal filter at the ISENS- pin, one capacitor, CT, is needed to match the time delay between the ISENS- and ISENS+ signals. Select the proper CT to keep the time constant of RISEN and CT (RISEN x CT) close to 27ns. Equation 7 shows that the ratio of the channel current to the sensed current, ISEN, is driven by the value of the sense resistor and the DCR of the inductor.
DCR I SEN = I L --------------R
ISEN
INDUCTOR DCR SENSING
An inductor's winding is characteristic of a distributed resistance, as measured by the DCR (Direct Current Resistance) parameter. Consider the inductor DCR as a separate lumped quantity, as shown in Figure 5. The channel current IL, flowing through the inductor, will also pass through the DCR. Equation 5 shows the s-domain equivalent voltage across the inductor VL.
V L ( s ) = I L ( s L + DCR ) (EQ. 5)
(EQ. 7)
RESISTIVE SENSING
For more accurate current sensing, a dedicated current-sense resistor RSENSE in series with each output inductor can serve as the current sense element (see Figure 7). This technique however reduces overall converter efficiency due to the additional power loss on the current sense element RSENSE.
IL L RSEN
VR VC(s) C ESL
A simple R-C network across the inductor extracts the DCR voltage, as shown in Figure 5.
VIN L
IL ( s ) DCR
VOUT COUT
ISL6596
INDUCTOR
C VL + +
VOUT COUT
VC(s)
RSENSE ISL6366
R ++
R
PWMS ISL6366
In RISEN(n) CURRENT SENSE
+ -
RISEN(n)
In CURRENT SENSE
+ 10.5
ISENS10.5
ISENS-
ISENS+
CT
ISENS+
CT
R SEN I SEN = I --------------------------------L 10.5 + R ISEN FIGURE 6. SENSE RESISTOR IN SERIES WITH INDUCTOR FOR VR1
DCR I SEN = I --------------------------------L 10.5 + R ISEN FIGURE 5. DCR SENSING CONFIGURATION FOR VR1
A current sensing resistor has a distributed parasitic inductance, known as ESL (equivalent series inductance, typically less than 1nH) parameter. Consider the ESL as a separate lumped quantity, as shown in Figure 7. The channel current IL, flowing through the inductor, will also pass through the ESL. Equation 8 shows the s-domain equivalent voltage across the resistor VR.
V R ( s ) = I L ( s ESL + R SEN ) (EQ. 8)
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A simple R-C network across the current sense resistor extracts the RSEN voltage, as shown in Figure 7. The voltage on the capacitor VC, can be shown to be proportional to the channel current IL. See Equation 9.
ESL s ------------- + 1 ( R SEN I L ) R SEN V C ( s ) = -------------------------------------------------------------------( s RC + 1 ) (EQ. 9)
The inductor DCR value will increase as the temperature increases. Therefore, the sensed current will increase as the temperature of the current sense element increases. In order to compensate the temperature effect on the sensed current signal, a Negative Temperature Coefficient (NTC) resistor can be used for thermal compensation, or the integrated temperature compensation function of ISL6366 should be utilized. The integrated temperature compensation function is described in "Temperature Compensation" on page 30. Decoupling capacitor (CT) on ISEN[6:1]- pins are optional and might be required for long sense traces and a poor layout.
I (s) L
L
ISL6366 In CURRENT SENSE
+ RISEN(n) R
C
ISEN-(n)
FIGURE 7. VOLTAGE ACROSS R WITHOUT RC I SEN = I DCR 64 ---------------------LR SET
ISEN+(n) RSET
FIGURE 9. DCR SENSING CONFIGURATION FOR VR0
FIGURE 8. VOLTAGE ACROSS C WITH MATCHING RC
Equation 10 shows that the ratio of the channel current to the sensed current, ISEN, is driven by the value of the sense resistor and the RISEN.
R SEN I SEN = I L --------------R (EQ. 10)
ISEN ISL6366 In CURRENT SENSE
+ RISEN(n)
IL L RSEN
VR VC(s) C ESL
RSENSE
R ++
Figures 5 and 6 configurations apply for VR1 output, while the RISEN should include the internal metal impedance of 10.5 for accurate current sense. For VR0 output, the RISEN resistor of each channel is integrated, while its value is determined by the RSET resistor. The RSET resistor value can be from 3.84k to 115.2k and is 64x of the required ISEN resistor value. Therefore, the current sense gain resistor (Integrated RISEN) value can be effectively set at 60 to 1.8k. Figures 9 and 10 show the configurations for inductor DCR sensing and resistive sensing of VR0, respectively; their sensing current is represented by Equations 11 and 12, respectively.
DCR 64 I SEN = I L ---------------------R
SET
ISEN-(n) ISEN+(n)
(EQ. 11)
R SEN 64 I SEN = I -----------------------L R SET
RSET
CT, Optional
R SEN 64 I SEN = I L -----------------------R
SET
(EQ. 12)
FIGURE 10. SENSE RESISTOR IN SERIES WITH INDUCTORS FOR VR0
18
-
Because of the internal filter at the ISENS- pin, one capacitor, CT, is needed to match the time delay between the ISENS- and ISENS+ signals. Select the proper CT to keep the time constant of RISEN and CT (RISEN x CT) close to 27ns.
VC(s)
+
-
+
If the R-C network components are selected such that the RC time constant matches the ESL-RSEN time constant (R*C = ESL/RSEN), the voltage across the capacitor VC is equal to the voltage drop across the RSEN, i.e., proportional to the channel current. As an example, a typical 1m sense resistor can use R = 348 and C = 820pF for the matching. Figures 7 and 8 show the sensed waveforms without and with matching RC when using resistive sense.
DCR
VOUT COUT
INDUCTOR
VL
CT, Optional
VOUT COUT
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ISL6366
L/DCR OR ESL/RSEN MATCHING
Assuming the compensator design is correct, Figure 11 shows the expected load transient response waveforms if L/DCR or ESL/RSEN is matching the R-C time constant. When the load current IOUT has a square change, the output voltage VOUT also has a square response, except for the overshoot at load release. However, there is always some PCB contact impedance of current sensing components between the two current sensing points; it hardly accounts into the L/DCR or ESL/RSEN matching calculation. Fine tuning the matching is necessarily done in the board level to improve overall transient performance and system reliability. If the R-C timing constant is too large or too small, VC(s) will not accurately represent real-time IOUT(s) and will worsen the transient response. Figure 12 shows the load transient response when the R-C timing constant is too small. VOUT will sag excessively upon load insertion and may create a system failure or early overcurrent trip. Figure 13 shows the transient response when the R-C timing constant is too large. VOUT is sluggish in drooping to its final value. There will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the CPU reliability.
IOUT
Channel-Current Balance for VR0
The sensed current In from each active channel is summed together and divided by the number of active channels. The resulting average current IAVG provides a measure of the total load current. Channel current balance is achieved by comparing the sensed current of each channel to the average current to make an appropriate adjustment to the PWM duty cycle of each channel with Intersil's patented current-balance method. Channel current balance is essential in achieving the thermal advantage of multiphase operation. With good current balance, the power loss is equally dissipated over multiple devices and a greater area.
Voltage Regulation
The compensation network shown in Figure 14 assures that the steady-state error in the output voltage is limited only to the error in the reference voltage (DAC & OFFSET) and droop current source, remote sense, and error amplifier. The sensed average current IDROOP is tied to FB internally and will develop voltage drop across the resistor between FB and VOUT for droop control. This current can be disconnected from the FB node by tying RFS_DRP high to VCC for non-droop applications. The output of the error amplifier, VCOMP, is compared to the internal sawtooth waveforms to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The ISL6366 does not have a unity gain amplifier in between the feedback path and error amplifier. For remote sensing, connect the microprocessor sensing pins to the non-inverting input, FB, via the feedback resistor (RFB), and inverting input, RGND, of the error amplifier. This configuration effectively removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point. VSEN should connect to remote sensing's positive rail as well for over voltage protection.
EXTERNAL CIRCUIT R C CC COMP ISL6366
VOUT
FIGURE 11. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
I OUT
V OUT
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN R-C TIME CONSTANT IS TOO SMALL
FB
IOUT
IDROOP ERROR AMPLIFIER RGND ++ VID & OFFSET VSEN + DAC OVP + VCOMP
VOUT
RFB
+ VDROOP -
FIGURE 13. LOAD TRANSIENT RESPONSE WHEN R-C TIME CONSTANT IS TOO LARGE
+-
VOUT
FIGURE 14. OUTPUT VOLTAGE AND LOAD-LINE REGULATION
A digital-to-analog converter (DAC) generates a reference voltage, which is programmable via SVID bus. The DAC decodes the SVID set command into one of the discrete voltages shown in Table 4. In addition, the output voltage can be margined in 5mV step between -640mV and 635mV, as shown in Table 5, via SVID set
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OFFSET command (33h). For a finer than 5mV offset, a large ratio resistor divider can be placed on the FB pin between the output and GND for positive offset or VCC for negative offset. VR1's VSENS, RGNDS, FBS, and COMPS pins function in the similar manner as VR0's VSEN, RGND, FB, and COMP pins.
TABLE 4. VR12/IMVP7 VID 8-BIT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 VOLTAGE OFF 0.2500 0.2550 0.2600 0.2650 0.2700 0.2750 0.2800 0.2850 0.2900 0.2950 0.3000 0.3050 0.3100 0.3150 0.3200 0.3250 0.3300 0.3350 0.3400 0.3450 0.3500 0.3550 0.3600 0.3650 0.3700 0.3750 0.3800 0.3850 0.3900 0.3950 0.4000 0.4050 0.4100 0.4150 0.4200 0.4250 TABLE 4. VR12/IMVP7 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D VOLTAGE 0.4300 0.4350 0.4400 0.4450 0.4500 0.4550 0.4600 0.4650 0.4700 0.4750 0.4800 0.4850 0.4900 0.4950 0.5000 0.5050 0.5100 0.5150 0.5200 0.5250 0.5300 0.5350 0.5400 0.5450 0.5500 0.5550 0.5600 0.5650 0.5700 0.5750 0.5800 0.5850 0.5900 0.5950 0.6000 0.6050 0.6100 0.6150 0.6200 0.6250 0.6300
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TABLE 4. VR12/IMVP7 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 HEX 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 VOLTAGE 0.6350 0.6400 0.6450 0.6500 0.6550 0.6600 0.6650 0.6700 0.6750 0.6800 0.6850 0.6900 0.6950 0.7000 0.7050 0.7100 0.7150 0.7200 0.7250 0.7300 0.7350 0.7400 0.7450 0.7500 0.7550 0.7600 0.7650 0.7700 0.7750 0.7800 0.7850 0.7900 0.7950 0.8000 0.8050 0.8100 0.8150 0.8200 0.8250 0.8300 0.8350 TABLE 4. VR12/IMVP7 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 38 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F VOLTAGE 0.8400 0.8450 0.8500 0.8550 0.8600 0.8650 0.8700 0.8750 0.8800 0.8850 0.8900 0.8950 0.9000 0.9050 0.9100 0.9150 0.9200 0.9250 0.9300 0.9350 0.9400 0.9450 0.9500 0.9550 0.9600 0.9650 0.9700 0.9750 0.9800 0.9850 0.9900 0.9950 1.0000 1.0050 1.0100 1.0150 1.0200 1.0250 1.0300 1.0350 1.0400
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TABLE 4. VR12/IMVP7 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 HEX A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 VOLTAGE 1.0450 1.0500 1.0550 1.0600 1.0650 1.0700 1.0750 1.0800 1.0850 1.0900 1.0950 1.1000 1.1050 1.1100 1.1150 1.1200 1.1250 1.1300 1.1350 1.1400 1.1450 1.1500 1.1550 1.1600 1.1650 1.1700 1.1750 1.1800 1.1850 1.1900 1.1950 1.2000 1.2050 1.2100 1.2150 1.2200 1.2250 1.2300 1.2350 1.2400 1.2450 TABLE 4. VR12/IMVP7 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 VOLTAGE 1.2500 1.2550 1.2600 1.2650 1.2700 1.2750 1.2800 1.2850 1.2900 1.2950 1.3000 1.3050 1.3100 1.3150 1.3200 1.3250 1.3300 1.3350 1.3400 1.3450 1.3500 1.3550 1.3600 1.3650 1.3700 1.3750 1.3800 1.3850 1.3900 1.3950 1.4000 1.4050 1.4100 1.4150 1.4200 1.4250 1.4300 1.4350 1.4400 1.4450 1.4500
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TABLE 4. VR12/IMVP7 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF VOLTAGE 1.4550 1.4600 1.4650 1.4700 1.4750 1.4800 1.4850 1.4900 1.4950 1.5000 1.5050 1.5100 1.5150 1.5200 OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 HEX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TABLE 5. VR12/IMVP7 635mV OFFSET 8-BIT OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 HEX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 VOLTAGE (mV) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D TABLE 5. VR12/IMVP7 635mV OFFSET 8-BIT (Continued) VOLTAGE (mV) 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200 205 210 215 220 225 230 235 240 245 250 255 260 265 270 275 280 285 290 295 300 305
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110
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TABLE 5. VR12/IMVP7 635mV OFFSET 8-BIT (Continued) OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 HEX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 VOLTAGE (mV) 310 315 320 325 330 335 340 345 350 355 360 365 370 375 380 385 390 395 400 405 410 415 420 425 430 435 440 445 450 455 460 465 470 475 480 485 490 495 500 TABLE 5. VR12/IMVP7 635mV OFFSET 8-BIT (Continued) OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 HEX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 38 89 8A 8B VOLTAGE (mV) 505 510 515 520 525 530 535 540 545 550 555 560 565 570 575 580 585 590 595 600 605 610 615 620 625 630 635 -640 -635 -630 -625 -620 -615 -610 -605 -600 -595 -590 -585
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TABLE 5. VR12/IMVP7 635mV OFFSET 8-BIT (Continued) OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 HEX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 VOLTAGE (mV) -580 -575 -570 -565 -560 -555 -550 -545 -540 -535 -530 -525 -520 -515 -510 -505 -500 -495 -490 -485 -480 -475 -470 -465 -460 -455 -450 -445 -440 -435 -430 -425 -420 -415 -410 -405 -400 -395 -390 TABLE 5. VR12/IMVP7 635mV OFFSET 8-BIT (Continued) OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 HEX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VOLTAGE (mV) -385 -380 -375 -370 -365 -360 -355 -350 -345 -340 -335 -330 -325 -320 -315 -310 -305 -300 -295 -290 -285 -280 -275 -270 -265 -260 -255 -250 -245 -240 -235 -230 -225 -220 -215 -210 -205 -200 -195
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TABLE 5. VR12/IMVP7 635mV OFFSET 8-BIT (Continued) OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0 HEX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF VOLTAGE (mV) -190 -185 -180 -175 -170 -165 -160 -155 -150 -145 -140 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
Load-Line Regulation
Some microprocessor manufacturers require a precisely controlled output resistance. This dependence of output voltage on load current is often termed "droop" or "load line" regulation. By adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction, which works to achieve the load-line regulation required by these manufacturers. In other cases, the designer may determine that a more costeffective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from fast load-current demand changes. The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. As shown in Figure 14, a current proportional to the average current of all active channels, IAVG, flows from FB through a loadline regulation resistor RFB. The resulting voltage drop across RFB is proportional to the output current, effectively creating an output voltage droop with a steady-state value defined, as shown in Equation 13:
V DROOP = I AVG R FB (EQ. 13)
The regulated output voltage is reduced by the droop voltage VDROOP. The output voltage as a function of load current is derived by combining Equation 13 with the appropriate sample current expression defined by the current sense method employed, as shown in Equation 14:
I LOAD R X V OUT = V REF - -------------- ----------------- R FB N R ISEN (EQ. 14)
where VREF is the reference voltage (DAC), ILOAD is the total output current of the converter, RISEN is the sense resistor connected to the ISEN+ pin, and RFB is the feedback resistor, N is the active channel number, and RX is the DCR, or RSENSE depending on the sensing method. Therefore, the equivalent loadline impedance, i.e. Droop impedance, is equal to Equation 15:
R FB R X R LL = ------------ ----------------N R ISEN (EQ. 15)
The major regulation error comes from the current sensing elements. To improve load-line regulation accuracy, a tight DCR tolerance of inductor or a precision sensing resistor should be considered.
Output-Voltage Offset Programming
The output voltage can be margined in 5mV steps between -640mV and 635mV, as shown in Table 5, via SVID set OFFSET command (33h). The minimum offset step is 5mV. For a finer than 5mV offset, a large ratio resistor divider can be placed on
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the FB pin between the output and GND for positive offset or VCC for negative offset. 1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold. Once this threshold is reached, proper operation of all aspects of the ISL6366 is guaranteed. Hysteresis between the rising and falling thresholds assure that once enabled, ISL6366 will not inadvertently turn off unless the bias voltage drops substantially (see "Electrical Specifications" table beginning on page 8). 2. The ISL6366 features an enable input (EN_PWR) for power sequencing between the controller bias voltage and another voltage rail. The enable comparator holds the ISL6366 in shutdown until the voltage at EN_PWR rises above 0.85V. The enable comparator has about 100mV of hysteresis to prevent bounce. It is important that the drivers reach their POR level before the ISL6366 becomes enabled. The schematic in Figure 15 demonstrates sequencing the ISL6366 with the ISL66xx family of Intersil MOSFET drivers. 3. The voltage on EN_VTT must be higher than 0.85V to enable the controller. This pin is typically connected to the output of VTT VR.
ISL6366 EXTERNAL CIRCUIT VCC +12V
Dynamic VID
Modern microprocessors need to make changes to their voltage as part of normal operation. They direct the core-voltage regulator to do this by making changes to the VID during regulator operation. The power management solution is required to monitor the DAC and respond to on-the-fly VID changes in a controlled manner. Supervising the safe output voltage transition within the DAC range of the processor without discontinuity or disruption is a necessary function of the core-voltage regulator. Three different slew rates can be selected during Dynamic VID (DVID) transition for VR0, but during VR0 soft-start, the setVID SLOW rate is defaulted. FDVID has no impact on VR1 rail, which can be 10mV/s minimum rate for setVID Fast, 2.5mV/s minimum rate for setVID Slow.
TABLE 6. SLEW RATE OPTIONS FDVID VR0 0 1 VR1 DON'T CARE SetVID FAST (Minimum Rate) 10mV/s 20mV/s 10mV/s SetVID SLOW (Minimum Rate) 2.5mV/s 5.0mV/s 2.5mV/s
POR CIRCUIT
ENABLE COMPARATOR + -
100k EN_PWR_CFP
During dynamic VID transition and VID step up, the overcurrent trip point increases by 140% to avoid falsely triggering OCP circuits, while the overvoltage trip point will follow the DAC+179mV level. If the dynamic VID occurs at PSI1/2/3/Decay (lower power state) asserted, the system should exit to PSI0 (full power state) and complete the transition, and will not resume the lowe power state operation unless the low power mode command is asserted again. In addition to ramping down the output voltage with a controlled rate as previously described, both VR0 and VR1 can be programmed into decay mode via SVID's setDecay command. Whenever the Decay command is received, the VR will enter PSI2 mode. The VR will be in single-phase operation. If the DE register is selected to be "Enable", the VR will operate in diode emulation mode and drop to the target voltage at a decay rate determined by the load impedance and output capacitive bank. The decay rate will be limited to 2.5mV/s rate setting. If the "DE" register is selected to be "Disable", then VR will drop at 2.5mV/s rate setting.
9.09k 0.85V
+ -
EN_VTT
0.85V SOFT-START AND FAULT LOGIC
FIGURE 15. POWER SEQUENCING USING THRESHOLDSENSITIVE ENABLE (EN) FUNCTION
Operation Initialization
Prior to converter initialization, proper conditions must exist on the enable inputs and VCC. When the conditions are met, the controller begins soft-start. Once the output voltage is within the proper window of operation, VR_RDY asserts logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a highimpedance state (or pulled to 40% of VCC) to assure the drivers remain off. The following input conditions must be met before the ISL6366 is released from shutdown mode.
When all conditions previously mentioned are satisfied, ISL6366 begins the soft-start and ramps the output voltage to the Boot Voltage set by hard-wired "BT" and "BTS" registers or first setVID command if boot voltage set to zero volts. After remaining at boot voltage for some time, ISL6366 reads the VID code via SVID bus. If the VID code is valid, ISL6366 will regulate the output to the final VID setting. If the VID code is "OFF" code, ISL6366 will remain shut down.
Soft-Start
ISL6366 based VR has 4 periods during soft-start, as shown in Figure 16. After VCC, EN_VTT and EN_PWR reach their POR/enable thresholds, the controller will have a fixed delay period tD1. After this delay period, the VR will begin first soft-start ramp until the output
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ISL6366
voltage reaches VBOOT voltage at a fixed slew rate, quarter of setVID FAST rate as in Table 6. Then, the controller will regulate the VR voltage at VBOOT for another period tD3 until SVID sends a new VID command. If the VID code is valid, ISL6366 will initiate the second soft-start ramp at a slew rate, set by SetDVID FAST or SLOW command in Table 6, until the voltage reaches the new VID voltage. The soft-start time is the sum of the 4 periods, as shown in Equation 16.
t SS = t D1 + t D2 + t D3 + t D4 (EQ. 16)
where VIMON is the voltage at the IMON pin, RIMON is the resistor between the IMON pin and GND, ILOAD is the total output current of the converter, RISEN is the sense resistor connected to the ISEN+ pin, N is the active channel number, and RX is the DC resistance of the current sense element, either the DCR of the inductor or RSENSE depending on the sensing method. The resistor from the IMON pin to GND should be chosen to ensure that the voltage at the IMON pin is typically 900mV at the maximum load current, typically corresponding to ICCMAX register. The IMON voltage is linearly digitized every 132s and stored in the IOUT register (15h). When the IMON voltage reaches 900mV or beyond, the digitized IOUT will be FFh and the Alert pin is pulled low to alarm the CPU. If the desired maximum load current alert is not the exact ICCMAX value, the IMON resistor can be scaled accordingly to make sure that it reaches 900mV at the desired maximum output load.I
0.9V R ISEN N R IMON = ----------------------------- -------------------------------------RX I DESIRED_MAX (EQ. 20)
tD1 is a fixed delay with the typical value as 4.6ms. tD3 is determined by the time to obtain a valid new VID voltage from SVID bus. If the VID is valid before the output reaches the boot voltage, the output will turn around to respond to the new VID code. During tD2 and tD4, ISL6366 digitally controls the DAC voltage change at 5mV per step. The soft-start ramp time tD2 and tD4 can be calculated based on Equations 17 and 18:
V BOOT t D2 = --------------------------------------------------- ( s ) SetVID SLOW RATE V VID - V BOOT t D4 = ----------------------------------- ( s ) SetVID RATE (EQ. 17) (EQ. 18)
A small capacitor can be placed between the IMON pin and GND to reduce the noise impact and do the average. The typical time constant is 1ms for VR12 applications. If this pin is not used, tie it to GND. In addition, if the IMON pin voltage is higher than 1.12V, overcurrent shutdown will be triggered, as described in "Overcurrent Protection" on page 29.
For example, when the VBOOT is set at 1.1V and setVID rate is set at 10mV/s, the first soft-start ramp time tD2 will be around 440s and the second soft-start ramp time tD4 will be at maximum of 40s if an setVID command for 1.5V is received after tD3. However, if VBOOT is set at 0V, the first setVID command is for 1.5V, then tD2 will be around 150s. Note that the initial 0 to 250mV DAC is typically at a slower rate to minimize the inrush current, the response time could be dictated by the compensation network and the output filter.
Fault Monitoring and Protection
The ISL6366 actively monitors output voltage and current to detect fault conditions. Fault monitors trigger protective measures to prevent damage to a microprocessor load. One common powergood indicator is provided for linking to external system monitors. The schematic in Figure 17 outlines the interaction between the fault monitors and the VR_RDY signal.
VR_Ready Signal
The VR_RDY pin is an open-drain logic output which indicates that the soft-start period is complete and the output voltage is within the regulated range. VR_RDY is pulled low during shutdown and releases high after a successful soft-start. VR_RDY will be pulled low when an fault (OCP or OVP) condition is detected, or the controller is disabled by a reset from EN_PWR, EN_VTT, POR, or VID OFF-code. If the Multi_VR_config register is set to 01h, then the VR_Ready line will stay high when receiving a 00h VID code after the first soft-start. The VR_RDYS behaves the same as VR_RDY, and both are independent from each other. However, the defaulted Multi_VR_config is 00h for VR0 and 01h for VR1.
tD1
tD2 EN_VTT
tD3 tD4
VR_Ready
FIGURE 16. SOFT-START WAVEFORMS
Current Sense Output
The current flowing out of the IMON pin is equal to the sensed average current inside ISL6366. In typical applications, a resistor is placed from the IMON pin to GND to generate a voltage, which is proportional to the load current and the resistor value, as shown in Equation 19:
R IMON R X V IMON = ------------------ ----------------- I LOAD N R ISEN (EQ. 19)
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6366 overvoltage protection (OVP) circuit will be active after its POR. The OVP thresholds are different under different operation conditions. When VR is not enabled and during the soft-start intervals tD1, the OVP threshold is 2.3V. Once the VR output voltage reaches above the DAC, fires the first PWM and completes the soft-start, the OVP trip point will change to a tacking level of DAC+179mV.
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Two actions are taken by ISL6366 to protect the microprocessor load when an overvoltage condition occurs. At the inception of an overvoltage event, all PWM outputs are commanded low instantly. This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level to avoid damaging the load. When the output voltage falls below the DAC plus 107mV, PWM signals enter a high-impedance state. The Intersil drivers respond to the high-impedance input by turning off both upper and lower MOSFETs. If the overvoltage condition reoccurs, ISL6366 will again command the lower MOSFETs to turn on. ISL6366 will continue to protect the load in this fashion as long as the overvoltage condition occurs. Once an overvoltage condition is detected, the respective VR# ceases the normal PWM operation and pulls its VR_Ready low until ISL6366 is reset. Cycling the voltage VCC below the POR-falling threshold will reset the controller. Cycling the EN_VTT, or EN_PWR will also reset the controller. average current is measured. The average current is continually compared with a constant 100A reference current, as shown in Figure 17. Once the average current exceeds the reference current, a comparator triggers the converter to shutdown. In addition, the current out of the IMON pin is equal to the sensed average current IAVG. With a resistor from IMON to GND, the voltage at IMON will be proportional to the sensed average current and the resistor value. The ISL6366 continuously monitors the voltage at the IMON pin. If the voltage at the IMON pin is higher than 1.12V, a precision comparator triggers the overcurrent shutdown. Since the internal current comparator has wider tolerance than the voltage comparator, the IMON voltage comparator is the preferred one for OCP trip. Hence, the resistor between IMON and GND can be scaled such that the overcurrent protection threshold is tripping lower than 100A. For example, the overcurrent threshold for the sensed average current IAVG can be set to 95A by using a 11.8k resistor from IMON to GND. Thus, the internal 100A comparator might only be triggered at its lower corner. However, IMON OCP trip should NOT be too far away from 140A, which is used for cycle-by-cycle protection and inductor saturation.
VR_RDY
OC
+ -
100A IAVG
OUTPUT CURRENT
SOFT-START, FAULT AND CONTROL LOGIC
0A
OUTPUT VOLTAGE VSEN
+ -
OV ISL6366
+
OC
1.12V
-
IMON
0V
2ms/DIV
VID + 0.179V
FIGURE 17. VR_RDY AND PROTECTION CIRCUITRY
FIGURE 18. OVERCURRENT BEHAVIOR IN HICCUP MODE. FSW = 500kHz
Overcurrent Protection
ISL6366 has two levels of overcurrent protection. Each phase is protected from a sustained overcurrent condition by limiting its peak current, while the combined phase currents are protected on an instantaneous basis. For the individual channel overcurrent protection, ISL6366 continuously compares the sensed peak current (~50ns filter) signal of each channel with the 140A reference current. If one channel current exceeds the reference current, ISL6366 will pull PWM signal of this channel to low for the rest of the switching cycle. This PWM signal can be turned on next cycle if the sensed channel current is less than the 140A reference current. The peak current limit of individual channel will only use for cycle-bycycle current limiting and will not trigger the converter to shutdown. In instantaneous protection mode, ISL6366 utilizes the sensed average current IAVG to detect an overcurrent condition. See "Current Sensing" on page 17 for more details on how the
At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state, commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFETs. The system remains in this state a period of 8ms. If the controller is still enabled at the end of this wait period, it will attempt a soft-start. If the fault remains, the trip-retry cycles will continue indefinitely (as shown in Figure 18) until either controller is disabled or the fault is cleared. Note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard during this kind of operation.
Thermal Monitoring (VR_HOT#)
VR_HOT# indicates the temperature status of the voltage regulator. VR_HOT# is an open-drain output, and an external pullup resistor is required. This signal is valid only after the controller is enabled. The VR_HOT# signal can be used to inform the system that the temperature of the voltage regulator is too high and the CPU should reduce its power consumption. The VR_HOT# signal may be tied to the CPU's PROC_HOT signal.
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VCC
Thermal Trip Point Lookup Table (90-1200C)
TMAX
+
TM
RTM TM
-
40.98%*VCC 39.12%*VCC
RNTC1
oc
VR_HOT#
VR_HOT# TEMPERATURE
T1 T2
RTMS TMS
oc
RNTC2
FIGURE 19. BLOCK DIAGRAM OF THERMAL MONITORING FUNCTION
The diagram of thermal monitoring function block is shown in Figure 19. One NTC resistor should be placed close to the respective power stage of the voltage regulator VR0 and VR1 to sense the operational temperature, and one pull-up resistor is needed to form the voltage divider for the TM pin. As the temperature of the power stage increases, the resistance of the NTC will reduce, resulting in the reduced voltage at the TM pin. Figure 20 shows the TM voltage over the temperature for a typical design with a recommended 6.8k NTC (P/N: NTHS0805N02N6801 from Vishay, = 3477) and 1k resistor RTM. It is recommended to use those resistors for the accurate temperature compensation since the internal thermal digital code is developed based upon these two components. If a different value is used, the temperature coefficient must be close to 3477 and RTM must be scaled accordingly. For instance, say NTC = 10k ( = 3477), then RTM should be 10k/6.8k*1k = 1.47k. There is a comparator with hysteresis to compare the TM pin voltage to the threshold set by the TMAX register for VR_HOT# signal. With TMAX set at +100C, the VR_HOT# signal is pulled to GND when either TM or TMS voltage is lower than 39.12% of VCC voltage, and is open when both TM and TMS voltages increase to above 40.98% of VCC voltage. The comparator trip point will be programmable by TMAX values. Figure 20 shows the operation of those signals.
100 90 80 VTM/VCC (%) 70 60 50 40 30 20 0 20 40 60 80 100 120 140
TEMPERATURE (oC)
FIGURE 20. THE RATIO OF TM VOLTAGE TO NTC TEMPERATURE WITH RECOMMENDED PARTS
+
NTC BETA ~ 3477
-
ISL6366
FIGURE 21. VR_HOT# SIGNAL (TMAX = 100C) vs TM VOLTAGE
Based on the NTC temperature characteristics and the desired threshold of the VR_HOT# signal, the pull-up resistor RTM of TM pin is given by Equation 21:
R TM = 1.557xR NTC ( T2 ) (EQ. 21)
RNTC(T2) is the NTC resistance at the VR_HOT# threshold temperature T2. The VR_HOT# is de-asserted at temperature T1, as shown in Table 7. Since the NTC directly senses the temperature of the PCB and not the exact temperature of the hottest component on the board due to airflow and varied thermal impedance, therefore, the user should select a lower TMAX number, depending upon the mismatching between NTC and the hottest components, than such component to guarantee a safe operation.
TABLE 7. VR_HOT# TYPICAL TRIP POINT AND HYSTERESIS TMAX (C) 90 95 100 105 110 115 120 VR_HOT# LOW (C; T2, %VCC) 88.6; 45.52% 94.3; 42.26% 100.0; 39.12% 106.1; 36.14% 109.1; 33.32% 115.5; 30.68% 118.7; 28.24% VR_HOT# OPEN (C; T1, %VCC) 85.9; 47.56% 91.4; 44.20% 97.1; 40.98% 103.0; 37.92% 106.1; 35.00% 112.3; 32.24% 115.5; 29.7% HYSTERESIS (C) 2.7 2.9 2.9 3.1 3.0 3.2 3.2
Temperature Compensation
The ISL6366 supports inductor DCR sensing, or resistive sensing techniques. The inductor DCR has a positive temperature coefficient, which is about +0.385%/C. Since the voltage across the inductor is sensed for the output current information, the sensed current has the same positive temperature coefficient as the inductor DCR. In order to obtain the correct current information, there should be a way to correct the temperature impact on the current sense component. ISL6366 provides two methods: integrated temperature compensation and external temperature compensation.
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Integrated Temperature Compensation
The ISL6366 utilizes the voltage at the TM pin and "TCOMP" register to compensate the temperature impact on the sensed current. The block diagram of this function is shown in Figure 22. channel and the output rail; DON'T place it close to the MOSFET side, which generates much more heat. ISL6366 multiplexes the "TCOMP" value with the TM digital signal to obtain the adjustment gain to compensate the temperature impact on the sensed channel current. The compensated channel current signal is used for droop and overcurrent protection functions.
TABLE 8. "TCOMP" AND "TCOMPS" VALUES TCOMP/TCOMPS (C) 13 16 18.9
PLACE NTC CLOSE TO CHANNLE 1 D/A
VCC
R TM
TM
ISL6366
NON-LINEAR A/D
CHANNEL CURRENT SENSE
Isen4 Isen3 Isen2 Isen1 I1
TCOMP/TCOMPS (C) 29.7 32.4 35.1 37.8 40.5 43.2 OFF
o
c
RNT C
I4
I3
I2
ki
21.6 24.3 27
4-BIT A/D
TCO MP
DROOP AND OVERCURRENT PROTECTION
FIGURE 22. BLOCK DIAGRAM OF INTEGRATED TEMPERATURE COMPENSATION
When the NTC is placed close to the current sense component (inductor), the temperature of the NTC will track the temperature of the current sense component. Therefore, the TM voltage can be utilized to obtain the temperature of the current sense component. Since the NTC could pick up noise from phase node, a 0.1F ceramic decoupling capacitor is recommended on the TM pin in close proximity to the controller. Based on the VCC voltage, the ISL6366 converts the TM pin voltage to a 6-bit TM digital signal for temperature compensation. With the non-linear A/D converter of ISL6366, the TM digital signal is linearly proportional to the NTC temperature. For accurate temperature compensation, the ratio of the TM voltage to the NTC temperature of the practical design should be similar to that in Figure 20.
When a different NTC type or different voltage divider is used for the TM function, the TCOMP voltage can also be used to compensate for the difference between the recommended TM voltage curve in Figure 20 and that of the actual design. If the same type NTC ( = 3477) but different value is used, the pull-up resistor needs to be scaled, as shown in Equation 22:
1k R NTC_NEW R TM = ------------------------------------------6.8k (EQ. 22)
Design Procedure
1. Properly choose the voltage divider for the TM pin to match the TM voltage vs temperature curve with the recommended curve in Figure 20. 2. Run the actual board under the full load and the desired cooling condition. 3. After the board reaches the thermal steady state, record the temperature (TCSC) of the current sense component (inductor or MOSFET) and the voltage at TM and VCC pins. 4. Use Equation 23 to calculate the resistance of the NTC, and find out the corresponding NTC temperature TNTC from the NTC datasheet or using Equation 24, where is equal to 3477 for recommended NTC.
V TM xR TM R NTC ( T NTC ) = ------------------------V CC - V
TM
VOUT
OUTPUT INDUCTOR NTC
PHASE1 POWER STAGE
(EQ. 23)
T NTC = -------------------------------------------------------------------- - 273.15 RTM ------------------------------- + -----------------ln R 298.15 NTC ( T NTC )
(EQ. 24)
FIGURE 23. RECOMMENDED PLACEMENT OF NTC
Since the NTC attaches to the PCB, but not directly to the current sensing component, it inherits high thermal impedance between the NTC and the current sensing element. The "TCOMP" register values can be utilized to correct the temperature difference between NTC and the current sense component. As shown in Figure 23, the NTC should be placed in proximity to the PSI
5. In Intersil designed worksheet, choose a number close to the result as in Equation 25 in the "TCOMP" cell to calculate the needed resistor network for the register "TCOMP" pin. (Note: for worksheet, please contact Intersil Application support at www.intersil.com/design/).
T COMP = T CSC - T NTC (EQ. 25)
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6. Run the actual board under full load again with the proper resistors connected to the "TCOMP" pin. 7. Record the output voltage as V1 immediately after the output voltage is stable with the full load. Record the output voltage as V2 after the VR reaches the thermal steady state. 8. If the output voltage increases over 2mV as the temperature increases, i.e. V2 - V1 > 2mV, reduce "TCOMP" value; if the output voltage decreases over 2mV as the temperature increases, i.e. V1 - V2 > 2mV, increase "TCOMP" values.
o
PH A SE
IS EN SC
ISL6366
External Temperature Compensation
When the "OFF" code of TCOMP is selected, then the internal current source is not thermally compensated, i.e, the integrated temperature compensation function is disabled. However, one external temperature compensation network, shown in Figure 24, can be used to cancel the temperature impact on the droop (i.e., load line).
ISEN S+
FIGURE 25. NTC WITH L/DCR MATCHING NETWORK FOR THERMAL COMPESNATION
COMP
ISL6366
IMON
ISL6366
FB
o
C
ID R O O P
o
C
VOUT
FIGURE 26. NTC WITH IMON NETWORK FOR THERMAL COMPESNATION
FIGURE 24. EXTERNAL TEMPERATURE COMPENSATION FOR LOAD LINE
The sensed current will flow out of the FB pin and develop a droop voltage across the resistor equivalent (RFB) between the FB pin and VOUT sensing node. If RFB resistance reduces as the temperature increases, the temperature impact on the droop can be compensated. An NTC resistor can be placed close to the power stage and used to form RFB. Due to the nonlinear temperature characteristics of the NTC, a resistor network is needed to make the equivalent resistance between the FB pin and VOUT sensing node inversely proportional to the temperature. This external temperature compensation network can only compensate the temperature impact on the droop, while it has no impact to the sensed current inside ISL6366. Therefore, this network cannot compensate for the temperature impact on the overcurrent protection function. In addition, NTC could pick up phase switching noise and easily inject into the loop. This method is typically not recommended. Furthermore, the NTC can be placed with L/DCR matching network to thermally compensate the sensed current, or with IMON network to thermally compensate the IMON voltage (typically need to set internal overcurrent trip higher than IMON OCP trip), as shown in Figures 25 and 26, respectively. These methods are typically applicable to both VR0 and VR1 for non-droop applications.
Hard-wired Registers (Patent Pending)
To set registers for VR12/IMVP7 applications using lowest pincount package and with lowest overall cost, Intersil has developed a high resolution ADC using a patented technique with simple 1%, 100ppm/k or better temperature coefficient resistor divider, as shown in Figure 27. The same type of resistors are preferred so that it has similar change over temperature. In addition, the divider is comparing to the internal divider off VCC and GND nodes and therefore must refer to VCC and GND pins, not through any RC decoupling network.
EXTERNAL CIRCUIT ISL6366 VCC
REGISTER TABLE ADC
RUP
RDW
FIGURE 27. SIMPLIFIED RESISTOR DIVIDER ADC
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There are total of four register pins to program the system parameters: Address OFFSET, setVID fast slew rate, boot voltage, ICCMAX, diode emulation option, number of phase operation at low power mode, and temperature compensation, as summarized in Table 9. Prior to the soft-start, the system parameters are stored in the SVID data registers of 0C, 0D, 0E, and 0F, respectively, as shown in Table 10. They are reset by Enable or VCC POR. In addition, data is available to verify the system setting over a high volume production. A design worksheet to select these pairs of resistors is available for use. Please contact Intersil Application support at www.intersil.com/design/. As an example, Table 11 shows the RUP and RDW values of each pin for a specific system design; DATA for corresponding registers can be read out via SVID's Get(reg) command. In addition, as shown in Table 12, some tie-high and tie-low options are for easy programming and can also be used to validate the VR operation during In-Circuit Test (ICT). For instance, when the system boot voltage is required at zero Volts, the BT_XX or BTS_XX pin can be tied to GND or VCC, prior to Enable, to get a known boot voltage to check VR operation with ICT.
TABLE 9. SYSTEM PARAMETER DESCRIPTION CODE NAME ADDR REG DESCRIPTION VR0/1 Address offset (VR0 and VR1 Are In Operation) VR0 Address offset (PWMS = VCC, FSS_DRPS = 1 M to GND) VR0 Address offset (PWMS=VCC, FSS_DRPS = 1 M to VCC) VR1 Address offset (PWM1 = VCC) BT VR0 Boot Voltages (RFS_DRP TIED GND) VR0 Boot Voltages (RFS_DRP TIED VCC) BTS VR1 Boot Voltages (RFSS_DRPS TIED GND) VR1 Boot Voltages (RFSS_DRPS TIED VCC) FDVID DE DES TMAX IMAX IMAXS setVID Fast Slew Rate for VR0 Diode Emulation Option of VR0 Diode Emulation Option of VR1 Maximum Operating Temperature ICCMAX of VR0 (5A/step) ICCMAX of VR1 (RFSS_DRPS TIED GND) ICCMAX of VR1 (RFSS_DRPS TIED VCC) NPSI Number of Operational Phases in PSI1/2/3/Decay States RANGE 0/1, 2/3 to 6/7 0, 2, 4, 6 8,A,C 1, 3, 5, 7 0, 0.9, 1.0, 1.1V 0,1.2, 1.35, 1.5V TABLE 12. TIE-HIGH AND TIE-LOW OPTIONS 0, 0.9, 1.0, 1.1V 0, 0.85, 0.925, 1.05V 0C 10mV/s, 20mV/s Enable, or Disable Enable, or Disable +90C to +120C (5C/Step) 15-165A (1:4-Phase); 105-255A (5:6-Phase) 20A, 25A, 30A, 35A 15A, 20A, 25A, 30A 1 or 2-Phase ADDR 0/1 0/1 6/7 6/7 BTS 0D
(RFSS_DRPS: GND/VCC)
TABLE 9. SYSTEM PARAMETER DESCRIPTION (Continued) CODE NAME TCOMP DESCRIPTION Mismatching Temperature Compensation between sensing element and NTC for VR0 Mismatching Temperature Compensation between sensing element and NTC for VR1 RANGE OFF, +13C to +43.2C
TCOMPS
OFF, +13C to +43.2C
TABLE 10. SYSTEM DATA REGISTER LOCATION REGISTER PIN NAME ADDR_IMAXS_TMAX BTS_DES_TCOMPS BT_FDVID_TCOMP NPSI_DE_IMAX DATA REGISTER CODE 0C 0D 0E 0F
TABLE 11. DESIGN EXAMPLE RUP ADDR 0/1 0D BTS 0.85V 0E BT 1.1V 0F NPSI SI1 IMAXS 25A DES ENABLED FDVID 20mV/s DE ENABLED TMAX +100C TCOMPS +29.7C TCOMP +29.7C IMAX 190A OPEN 10k 00h 10k OPEN DFh 255k 140k C0h 29.4k 15k 08h RDW DATA
0C
REG IMAXS
(RFSS_DRPS: GND/VCC)
RUP
RDW
DATA
TMAX +100C +95C +100C +95C 10k OPEN OPEN 10k 0h 1Fh C0h DFh
35A/30A 20A/15A 35A/30A 20A/15A
499k OPEN OPEN 499k
DES DISABLED ENABLED DISABLED ENABLED
TCOMPS +29.7C +29.7C +29.7C OPEN 10k 10k OPEN 00h 1Fh C0h DFh
1.1V/1.5V 1.1V/1.5V 0 0
OPEN 499k
+29.7C 499k OPEN
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TABLE 12. TIE-HIGH AND TIE-LOW OPTIONS (Continued) REG IMAXS 0C 0E ADDR BT (RFS_DRP:
GND/VCC) (RFSS_DRPS: GND/VCC)
.
RUP
RDW
DATA
VOUT C
RFBS IRC IDVC
IDVC = IC
IC R CC RC COMP
TMAX TCOMP 29.7C 29.7C 29.7C 29.7C IMAX 190A 255A 190A 255A OPEN 10k 10k OPEN 00h 1Fh C0h DFh OPEN 10k 10k OPEN 00h 1Fh C0h DFh
VDAC DVC CDVC
RDVC
FDVID 10mV/s 20mV/s 10mV/s 20mV/s DE ENABLED ENABLED DISABLED DISABLED
FB
1.1V/1.05V 1.1V/1.05V 0 0 0F NPSI SI1/CI1 SI1/CI1 SI2/CI2 SI2/CI2
x1.333
+
ERROR AMPLIFIER
OPEN 499k 499k OPEN
IRC+IDROOP_ACTUAL ISL6366 INTERNAL CIRCUIT
FIGURE 28. DYNAMIC VID COMPENSATION NETWORK
OPEN 499k 499k OPEN
NOTE: Whenever 10k is tie-high or tie-low, 0 can be used.
Dynamic VID Compensation (DVC)
During a VID transition, the resulting change in voltage on the FB pin and the COMP pin causes an AC current to flow through the error amplifier compensation components from the FB to the COMP pin. This current then flows through the feedback resistor, RFB, and can cause the output voltage to overshoot or undershoot at the end of the VID transition. In order to ensure the smooth transition of the output voltage during a VID change, a VID-on-the-fly compensation network is required. This network is composed of a resistor and capacitor in series, RDVC and CDVC, between the DVC and the FB pin. This VID-on-the-fly compensation network works by sourcing AC current into the FB node to offset the effects of the AC current flowing from the FB to the COMP pin during a VID transition. To create this compensation current, the controllers set the voltage on the DVC pin to be 4/3 of the voltage on the DAC. Since the error amplifier forces the voltage on the FB pin and the DAC to be equal, the resulting voltage across the series RC between DVC and FB is equal to the DAC voltage. The RC compensation components, RDVC and CDVC, can then be selected to create the desired amount of compensation current.
The amount of compensation current required is dependant on the modulator gain of the system, K1, and the error amplifier R-C components, RC and CC, that are in series between the FB and COMP pins. Use Equations 26, 27, and 28 to calculate the RC component values, RDVC and CDVC, for the VID-on-the-fly compensation network. For these equations: VIN is the input voltage for the power train; VRAMP is the oscillator ramp amplitude as in Equation 3; and RC and CC are the error amplifier R-C components between the FB and COMP pins.
V IN K1 = ----------------V RAMP R DVC = A R C CC C DVC = ----A K1 A = ----------------------------3 ( K1 - 1 ) (EQ. 26)
(EQ. 27) (EQ. 28)
During DVID transitions, extra current builds up in the output capacitors due to the C*dv/dt. The current is sensed by the controller and fed across the feedback resistor creating extra droop (if enabled) and causing the output voltage not properly tracking the DAC voltage. Placing a series R-C to ground from the FB pin can sink this extra DVID induced current.
C OUT R LL C = --------------------------R FB C OUT R LL R = -------------------------- = R FB C (EQ. 29)
(EQ. 30)
When the output voltage overshoots during DVID, the RDVC-CDVC network can be used to compensate the movement of the error-amplifier compensation network. When the output voltage is lagging from DAC (or SVALERT#) or having a rough-off prior to the final settling of DVID, the R-C network can be used to compensate for the extra droop current generated by the C*dv/dt. Sometimes, both networks can work together to achieve the best result. In such case, both networks need to be fine tuned in the board level for optimized performance.
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ISL6366 Disabling Output
When disabling any output, its respective pins should be tied accordingly as in Table 13. However, when both outputs are fully populated, pulling the respective PWM line to VCC should be sufficient.
TABLE 13. DISABLE OUTPUT CONFIGURATION DISABLE VR1 OUTPUT PIN NAME PWMS RNGDS; VSENS; FBS; IMONS; ISENS-; VR_RDYS HFCOMPS/DVCS; ISENS+ FSS_DRPS TMS PIN CONFIGURATION VCC GND
schematics, bills of materials, and example board layouts for common microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to determine the number of phases. This determination depends heavily upon the cost analysis, which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power supply circuitry. Generally speaking, the most economical solutions are those in which each phase handles between 15A and 25A. All surface-mount designs will tend toward the lower end of this current range. If through-hole MOSFETs and inductors can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors and heatdissipating surfaces.
OPEN 1Mto GND (for 0, 2, 4, 6 ADDR) or 1M to VCC for 8, A, C ADDR) Connect To TM pin or a 1/2 ratio Resistor Divider (1M/2M) to avoid tripping VR_HOT#; or Use it as a second thermal sensing for VR_HOT#. DON'T tie it to VCC or GND. DISABLE VR0 OUTPUT
MOSFETs
The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate heat; and the availability and nature of heat sinking and air flow. Lower MOSFET Power Calculation The calculation for heat dissipated in the lower MOSFET is simple, since virtually all of the heat loss in the lower MOSFET is due to current conducted through the channel resistance (rDS(ON)). In Equation 31, IM is the maximum continuous output current; IPP is the peak-to-peak inductor current (see Equation 1 on page 14); d is the duty cycle (VOUT/VIN); and L is the perchannel inductance.
2 I M 2 I PP P LOW, 1 = r DS ( ON ) ----- + --------- ( 1 - d ) 12 N
PIN NAME PWM1 RNGD; VSEN; FB; IMON; ISEN[1:4]-; VR_RDY HFCOMP; DVC; ISEN[1:6]+ FS_DRP, RSET TM
PIN CONFIGURATION VCC GND
OPEN 1M to GND Connect To TMS pin or a 1/2 ratio Resistor Divider (1M/2M) to avoid tripping VR_HOT#; or Use it as a second thermal sensing for VR_HOT#. DON'T tie it to VCC or GND.
(EQ. 31)
SVID Operation
The device is fully compliant with Intel VR12/IMVP7 SVID protocol Rev 1.5, document# of 456098. To ensure proper CPU operation, refer to this document for SVID bus design and layout guidelines; each platform requires different pull-up impedance on the SVID bus, while impedance matching and spacing among DATA, CLK, and ALERT# signals must be followed. Common mistakes are insufficient spacing among signals and improper pull-up impedance. A simple operational instruction of SVID bus with Intel VTT Tool is documented in "VR12 Design and Validation" in Table 15.
An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at IM, VD(ON); the switching frequency, Fsw; and the length of dead times, td1 and td2, at the beginning and the end of the lower-MOSFET conduction interval respectively.
I IM M I PP t P LOW, 2 = V D ( ON ) F SW ----- + I PP t N- -------- d1 + ----- - -------- d2 2 2 N (EQ. 32)
Finally, the power loss of output capacitance of the lower MOSFET is approximated in Equation 33:
2 1.5 P LOW ,3 -- V IN C OSS_LOW V DS_LOW F SW 3 (EQ. 33)
General Design Guide
This design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs, which include
where COSS_LOW is the output capacitance of lower MOSFET at the test voltage of VDS_LOW. Depending on the amount of ringing, the actual power dissipation will be slightly higher than this.
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Thus the total maximum power dissipated in each lower MOSFET is approximated by the summation of PLOW,1, PLOW,2 and PLOW,3. Upper MOSFET Power Calculation In addition to rDS(ON) losses, a large portion of the upper-MOSFET losses are due to currents conducted across the input voltage (VIN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times; the lower-MOSFET body-diode reverse-recovery charge, Qrr; and the upper MOSFET rDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 34, the required time for this commutation is t1 and the approximated associated power loss is PUP,1.
I M I PP t 1 P UP,1 V IN ----- + -------- ---- F SW N2 2 (EQ. 34)
The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 34 to 39. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies.
Current Sensing Resistor
The resistors connected to the ISEN+ pins determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. Select values for these resistors by using Equation 40:
RX I - OCP R ISEN = -------------------------- -----------6 N 100 x10 (EQ. 40)
where RISEN is the sense resistor connected to the ISEN+ pin, N is the active channel number, RX is the resistance of the current sense element, either the DCR of the inductor or RSENSE depending on the sensing method, and IOCP is the desired overcurrent trip point. Typically, IOCP can be chosen to be 1.2 times the maximum load current of the specific application. With integrated temperature compensation, the sensed current signal is independent of the operational temperature of the power stage, i.e. the temperature effect on the current sense element RX is cancelled by the integrated temperature compensation function. RX in Equation 40 should be the resistance of the current sense element at the room temperature. When the integrated temperature compensation function is disabled by selecting "OFF" TCOMP code, the sensed current will be dependent on the operational temperature of the power stage, since the DC resistance of the current sense element may be changed according to the operational temperature. RX in Equation 40 should be the maximum DC resistance of the current sense element at the all operational temperature. In certain circumstances, especially for a design with an unsymmetrical layout, it may be necessary to adjust the value of one or more ISEN resistors for VR0. When the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run cooler than the average, choose new, larger values of RISEN for the affected phases (see the section entitled "Current Sensing" on page 17). Choose RISEN,2 in proportion to the desired increase in temperature rise in order to cause proportionally more current to flow in the cooler phase, as shown in Equation 41:
T 2 R ISEN,2 = R ISEN ---------T 1 R ISEN = R ISEN,2 - R ISEN (EQ. 41)
At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 35, the approximate power loss is PUP,2.
I M I PP t 2 P UP, 2 V IN ----- - -------- ---- F SW 2 2 N (EQ. 35)
A third component involves the lower MOSFET's reverse-recovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lower-MOSFET's body diode can draw all of Qrr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is PUP,3 and is approximated in Equation 36:
P UP,3 = V IN Q rr F SW (EQ. 36)
The resistive part of the upper MOSFET's is given in Equation 37 as PUP,4.
2 I PP I M P UP,4 r DS ( ON ) ----- + --------- d 12 N 2
(EQ. 37)
Equation 38 accounts for some power loss due to the drainsource parasitic inductance (LDS, including PCB parasitic inductance) of the upper MOSFETs, although it is not the exact:
I I PP M P UP,5 L DS ----- + -------- 2 N
2
(EQ. 38)
Finally, the power loss of output capacitance of the upper MOSFET is approximated in Equation 39:
2 1.5 P UP,6 -- V IN C OSS_UP V DS_UP F SW 3 (EQ. 39)
where COSS_UP is the output capacitance of lower MOSFET at test voltage of VDS_UP. Depending on the amount of ringing, the actual power dissipation will be slightly higher than this. 36
In Equation 41, make sure that T2 is the desired temperature rise above the ambient temperature, and T1 is the measured temperature rise above the ambient temperature. Since all channels' RISEN are integrated and set by one RSET, a resistor (RISEN) should be in series with the cooler channel's ISEN+ pin to raise this phase current. While a single adjustment according to Equation 41 is usually sufficient, it may occasionally be necessary
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to adjust RISEN two or more times to achieve optimal thermal balance between all channels. output-voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount, as shown in Equation 45:
di V ( ESL ) ---- + ( ESR ) I dt (EQ. 45)
Load-Line Regulation Resistor
The load-line regulation resistor is labelled RFB in Figure 14. Its value depends on the desired loadline requirement of the application. The desired loadline can be calculated using Equation 42:
V DROOP R LL = -----------------------I FL (EQ. 42)
The filter capacitor must have sufficiently low ESL and ESR so that V < VMAX. Most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited highfrequency performance. Minimizing the ESL of the highfrequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see "Interleaving" on page 14 and Equation 2), a voltage develops across the bulk-capacitor ESR equal to IC,PP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the lower limit on the inductance, as shown in Equation 46.
V OUT K RCM L ESR --------------------------------------------------------F SW V IN V (EQ. 46)
where IFL is the full load current of the specific application, and VRDROOP is the desired voltage droop under the full load condition. Based on the desired loadline RLL, the loadline regulation resistor can be calculated using Equation 43:
N R ISEN R LL R FB = -------------------------------------RX (EQ. 43)
where N is the active channel number, RISEN is the sense resistor connected to the ISEN+ pin, and RX is the resistance of the current sense element, either the DCR of the inductor or RSEN depending on the sensing method. If one or more of the current sense resistors are adjusted for thermal balance (as in Equation 41), the load-line regulation resistor should be selected based on the average value of the current sensing resistors, as given in Equation 44:
R LL R FB = -------RX
PP( MAX )
RISEN ( n )
n
(EQ. 44)
where RISEN(n) is the current sensing resistor connected to the nth ISEN+ pin.
Output Filter Design
The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can respond. Because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. The output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, I; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total 37
Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than VMAX. This places an upper limit on inductance. Equation 47 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater outputvoltage deviation than the leading edge. Equation 48 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels.
2 N C V OUT L -------------------------------------- V MAX - I ESR ( I ) 2 NC L 1.25 ---------------------------- V MAX - I ESR V IN - V OUT ( I ) 2 (EQ. 47) (EQ. 48)
Switching Frequency Selection
There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upperMOSFET loss calculation. These effects are outlined in "MOSFETs" on page 35, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output-voltage ripple as outlined in "Output Filter Design" on page 37. Choose the lowest switching
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INPUT-CAPACITOR CURRENT (IRMS/IO)
frequency that allows the regulator to meet the transient-response and output-voltage ripple requirements. To minimize the effect of cross coupling between regulators, select operating frequencies of VR0 and VR1 at least 50kHz apart.
0.3
IL,PP = 0 IL,PP = 0.25 IO
IL,PP = 0.5 IO IL,PP = 0.75 IO
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. The input RMS current can be calculated with Equation 49.
I IN, RMS = K IN, CM =
2 2 2 K IN, CM * Io 2 + K RAMP, CM * I Lo, PP
0.2
0.1
(EQ. 49) (EQ. 50)
0
(N * D - m + 1) * (m - N * D) -------------------------------------------------------------------------N2
0
0.2
0.4 0.6 DUTY CYCLE (VOUT/VIN)
0.8
1.0
K RAMP, CM =
0.3 INPUT-CAPACITOR CURRENT (IRMS/IO)
INPUT-CAPACITOR CURRENT (IRMS/IO)
m2 ( N * D - m + 1 )3 + ( m - 1 )2 ( m - N * D )3 -----------------------------------------------------------------------------------------------------------------12N 2 D 2 (EQ. 51)
FIGURE 30. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 3-PHASE CONVERTER
0.3 IL,PP = 0 IL,PP = 0.25 IO IL,PP = 0.5 IO IL,PP = 0.75 IO
0.2
0.2
0.1
0.1 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0 0.2 0.4 0.6 DUTY CYCLE (VOUT/VIN) 0.8 1.0
0
0
0.2
0.4 0.6 DUTY CYCLE (VOUT/VIN)
0.8
1.0
FIGURE 31. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 4-PHASE CONVERTER
FIGURE 29. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR 2-PHASE CONVERTER
For a 2-phase design, use Figure 29 to determine the input capacitor RMS current requirement given the duty cycle, maximum sustained output current (IO), and the ratio of the per-phase peak-to-peak inductor current (IL,PP) to IO. Select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage.
Figures 27 and 28 provide the same input RMS current information for 3 and 4-phase designs respectively. Use the same approach to selecting the bulk capacitor type and number as previously described. Low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. The result from the high current slew rates produced by the upper MOSFETs turn on and off. Select low ESL ceramic capacitors and place one as close as possible to each upper MOSFET drain to minimize board parasitic impedances and maximize noise suppression.
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0.6 INPUT-CAPACITOR CURRENT (IRMS/IO)
TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION
(Continued)
PIN NAME NOISE SENSITIVITY No DESCRIPTION Open Pin. Reserved for "ISENIN+" in ISL6366A/67: It will be noise sensitive and connects to the Drain of High-side MOSFET side of the input inductor or resistor pin. There is an internal 1s filter. Decoupling capacitor is NOT needed, but if needed, use a low time constant one to avoid too much of shut-down delay. It will also be the output of CFP function in ISL6366A and ISL6367: 34 strong pull-up. 25 mils spacing from other traces. NO decoupling capacitor allowed on this pin, but decoupling its resistor pull-up RAIL with a high quality ceramic capacitor (0.1F or higher) or with very small RC filter (<2.2s). Pairing up with the positive rail remote sensing line that connected to FB resistor, and routing them to the load sensing points. Used for Overvoltage protection sensing only, and it has 1s internal filter. Decoupling is NOT needed. Add a 0 series impedance to be compatible with ISL6366A/67. Pairing up with the negative rail of remote sensing line that connected to RGND, and routing them to the load sensing points. Reserve an RC from FB to GND to compensate the output lagging from DAC during DVID transitions. Connect an R to the VR0 output. The R value is typically equal or slightly higher than the feedback resistor (droop resistor), fine tuned according to the high frequency transient performance. Placing the compensation network in close proximity to the controller. The series impedance typically should be 2x-3x the impedance in type III compensation to reduce noise coupling. Placing the compensation network in close proximity to the controller. Placing the compensation network in close proximity to the controller. Typically use a 68pF or higher across FB to COMP depending upon the noise coupling of the layout. 4/3 of DAC voltage. Placing the compensation network in close proximity to the controller. Referring to GND, not RGND. Place R and C in general proximity to the controller. The time constant of RC should be sufficient, typically 1ms, as an average function for the digital IOUT of VR0.
0.4
NC5
0.2 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0 0.2 0.4 0.6 DUTY CYCLE (VOUT/VIN) 0.8 1.0
EN_PWR
No
FIGURE 32. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY CYCLE FOR SINGLE-PHASE CONVERTER
RAMP_ADJ
Yes
MULTIPHASE RMS IMPROVEMENT
Figure 32 is provided as a reference to demonstrate the dramatic reductions in input-capacitor RMS current upon the implementation of the multiphase topology. For example, compare the input RMS current requirements of a 2-phase converter versus that of a single phase. Assume both converters have a duty cycle of 0.25, maximum sustained output current of 40A, and a ratio of IL,PP to IO of 0.5. The single phase converter would require 17.3ARMS current capacity while the 2-phase converter would only require 10.9ARMS. The advantages become even more pronounced when output current is increased and additional phases are added to keep the component cost down relative to the single phase approach.
RGND Yes
VSEN
No
FB
Yes
Layout and Design Considerations
The following layout and design strategies are intended to minimize the noise coupling, the impact of board parasitic impedances on converter performance and to optimize the heat-dissipating capabilities of the printed-circuit board. These sections highlight some important practices which should follow during the layout process. A layout check list in excel format is available for use.
HFCOMP Yes
Pin Noise Sensitivity, Design and Layout Consideration
Table 14 shows the noise sensitivity of each pin and their design and layout consideration. All pins and external components should not be across switching nodes and placed in general proximity to the controller.
TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION NOISE SENSITIVITY No
PSICOMP
Yes
COMP
Yes
PIN NAME NC4
DESCRIPTION Open Pin. Reserved for "ISENIN-" in ISL6366A/67: It will be noise sensitive and connect to input supply side of the input inductor or resistor pin with L/DCR or ESL/R matching network in close proximity to the controller. Place NTC in the close proximity to input inductor for thermal compensation.
DVC
Yes
IMON
Yes
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TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION
(Continued)
PIN NAME SVDATA; SVCLK NOISE SENSITIVITY Yes DESCRIPTION 13 to 26MHz signals when the SVID bus is sending commands, pairing up with SVALERT# and routing carefully back to CPU socket. 20 mils spacing within SVDATA, SVALERT#, and SVCLK; and more than 30 mils to all other signals. Refer to the Intel individual platform design guidelines and place proper terminated (pull-up) resistance for impedance matching. Local decoupling capacitor is needed for the pull-up rail. Open drain and high dv/dt pin during transitions. Routing it in the middle of SVDATA and SVCLK. Also see above. Open drain and high dv/dt pin. Avoid its pull-up higher than VCC. Tie it to ground when not used. Floating Pins. Reserved pull-up resistors for I2C/PMBus in ISL6367A: I2CLK pin, it will be noise sensitive. 100kHz to 2MHz signal when the I2C or PMBus is sending commands, pairing up with PMALERT# and routing carefully back to PMBus. 20 mils spacing within I2DATA, PMALERT#, and I2CLK; and more than 30 mils to all other signals. Refer to the PMBus design guidelines and place proper terminated (pull-up) resistance for impedance matching. Floating Pins. Reserved pull-up resistors for I2C/PMBus in ISL6367: I2DATA pin, it will be noise sensitive. Also see above. Floating Pins. Reserved pull-up resistors for PMBus in ISL6367: PMALERT# pin. Also see above. Referring to GND, not RGNDS. Place R and C in general proximity to the controller. The time constant of RC should be sufficient, typically 1ms, as an average function for the digital IOUT of VR1. Open drain and high dv/dt pin during transitions. Avoid its pull-up rail higher than VCC. 30 mils spacing from other traces. Connect an R in similar value (equal or slight higher) of the feedback resistor. If programmed to be used as DVCS, Connect an RC to FBS from this pin. Placing the compensation network in close proximity to the controller. Open drain and high dv/dt pin. Avoid its pull-up higher than VCC. Tie it to GND when not used. PIN NAME COMPS
(Continued)
NOISE SENSITIVITY Yes DESCRIPTION Placing the compensation network in close proximity to the controller. Typically use a 68pF or higher across FBS to COMPS depending upon the noise coupling of the layout. Pairing up with the negative rail of remote sensing line that connected to RGNDS, and routing them to the load sensing points. Reserve an RC from FBS to GND to compensate the output lagging from DAC during DVID transitions. Used for Overvoltage protection sensing only, and it has 1s internal filter. Decoupling is NOT needed. Add a series impedance to be compatible with ISL6366A/67. Pairing up with the positive rail remote sensing line that connected to FB resistor, and routing them to the load sensing points. Yes Placing the R in close proximity to the controller. Avoid using decoupling capacitor on this pin. Must tie GND or VCC via 1M depending upon the desired ADDRESS offset when VR1 is not in use. Don't use decoupling capacitor on this pin. To minimize the effect of cross coupling between regulators, select operating frequencies of VR0 and VR1 at least 50kHz apart. Placing NTC in close proximity to the output inductor of VR1 and to the output rail, not close to MOSFET side (see Figure 23); the return trace should be 25 mils away from other traces. Place 1k pullup and decoupling capacitor (typically 0.1F) in close proximity to the controller. The pull-up resistor should be exactly tied to the same point as VCC pin, not through an RC filter. If not used, connect this pin to TM or 1M/2M resistor divider, but DON'T tie it to VCC or GND. Place the NTC in proximity to the output rail, not close to MOSFET side. Yes Connect to the output rail side of the output inductor or current sensing resistor pin with ISEN resistor and decoupling capacitor (27ns) placed in close proximity to the controller. Connect to the phase node side of the output inductor or resistor pin with L/DCR or ESL/RSEN matching network in close proximity to the ISENS pins of the controller. Differential pair with ISENS+ routing back to the controller.
FBS
Yes
SVALERT#
No
VSENS
No
VR_RDY
No
RGNDS
NC3
No
FSS_DDRS
NC1
No
TMS
NC2
No
IMONS
Yes
VR_HOT#
No
ISENS+
HFCOMPS/D VCS
Yes
ISENS-
Yes
VR_RDYS
No
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TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION TABLE 14. PIN DESIGN AND/OR LAYOUT CONSIDERATION
(Continued)
PIN NAME PWMS NOISE SENSITIVITY No DESCRIPTION Avoid the routing across or under other phase's power trains and DCR sensing network. Don't make them across or under external components of the controller. At least 30mils away from any other traces. Register setting is locked prior to soft-start. Since the external resistor-divider ratio compares with the internal resistor ratio of the VCC, their rail should be exactly tied to the same point as VCC pin, not through an RC filter. DON'T use decoupling capacitors on these pins. Placing NTC in close proximity to the output inductor of VR0's Channel 1 and to the output rail, not close to MOSFET side (see Figure 23); the return trace should be 25 mils away from other traces. Place 1k pull-up and decoupling capacitor (typically 0.1F) in close proximity to the controller. The pull-up resistor should be exactly tied to the same point as VCC pin, not through an RC filter. If not used, connect this pin to TMS or 1M /2M resistor divider, but DON'T tie it to VCC or GND. No Program SI (standard-inductor, tied to GND) and CI (coupled inductor, tied to VCC). It is reserved for IAUTO in ISL6366A/67 and will be noise sensitive; SI and CI are still programmable with this pin. Placing the R in close proximity to the controller. DON'T use decoupling capacitor on this pin. Placing the R in close proximity to the controller. Must tie GND or VCC via 1M when VR0 is not in use. Don't use decoupling capacitor on this pin. Place the decoupling capacitor in close proximity to the controller. Avoid the respective PWM routing across or under other phase's power trains/planes and current sensing network. Don't make them across or under external components of the controller. At least 20mils away from any other traces. There is an internal 1s filter. Decoupling capacitor is not needed, but if needed, use a low timing constant one to avoid too much shut-down delay. Connect to the output rail side of the respective channel's output inductor or resistor pin. Decoupling is optional and might be required for long sense traces and a poor layout. GND PIN NAME ISEN[6:1]-
(Continued)
NOISE SENSITIVITY Yes DESCRIPTION Connect to the phase node side of the respective channel's output inductor or resistor pin with L/DCR or ESL/RSEN matching network in close proximity to the ISEN pins of VR0. Differentially routing back to the controller by paring with respective ISEN+; at least 20 mils spacing between pairs and away from other traces. Each pair should not across the other channel's switching nodes [Phase, UGATE, LGATE] and power planes even though they are not in the same layer This EPAD is the return of PWM output drivers and SVID bus. Use 4 or more vias to directly connect the EPAD to the power ground plane. Avoid using only single via or 0 resistor connection to the power ground plane. The layer next to the Top or Bottom layer is preferred to be ground players, while the signal layers can be sandwiched in the ground layers if possible.
ADDR_XX; NPSI_XX; BT_XX; BTS_XX
No
TM
Yes
General Comments
Component Placement
Within the allotted implementation area, orient the switching components first. The switching components are the most critical because they carry large amounts of energy and tend to generate high levels of noise. Switching component placement should take into account power dissipation. Align the output inductors and MOSFETs such that space between the components is minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. If possible, duplicate the same placement of these components for each phase. Next, place the input and output capacitors. Position the highfrequency ceramic input capacitors next to each upper MOSFET drain. Place the bulk input capacitors as close to the upper MOSFET drains as dictated by the component size and dimensions. Long distances between input capacitors and MOSFET drains result in too much trace inductance and a reduction in capacitor performance. Locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket. To improve the chance of first pass success, it is very important to take time to follow the above outlined design guidelines and Intersil generated layout check list, see more details in "VoltageRegulator (VR) Design Materials" on page 42. Proper planning for the layout is as important as designing the circuits. Running things in a hurry, you could end up spending weeks and months to debug a poorly-designed and improperly laid out board.
SICI
RSET
Yes
FS_DRP
Yes
VCC PWM1-6
Yes NO
EN_VTT
No
ISEN[6:1]+
Yes
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FN6964.0 January 3, 2011
ISL6366 Powering Up And Open-Loop Test
The ISL6366 features very easy debugging and powering up. For the first-time powering up, an open-loop test can be done by applying sufficient voltage (current limiting to 0.25A) to VCC, proper pull-up to SVID bus, and signal high to EN_VTT and EN_PWR pins with the input voltage (VIN) disconnected. 1. Each PWM output should operate at maximum duty cycle (typically VR0 at 98% and VR1 at 83%) and correct switching frequency. 2. The 0C, 0D, 0E, and 0F registers can be read via SVID bus to check its proper setting if an VTT tool is installed and operating. 3. If 5V drivers are used and share the same rail as VCC, the proper switching on UGATEs and LGATEs should be seen. 4. If 12V drivers are used and can be disconnected from VIN and sourced by an external 12V supply, the proper switching on UGATEs and LGATEs should be observed. 5. If the above is not properly operating, you should check soldering joint, resistor register setting, Power Train connection or damage, i.e, shorted gates, drain and source. Sometimes the gate might be measured short due to residual gate charge. Therefore, a measured short gate with ohmmeter cannot validate if the MOSFET is damaged unless the Drain to Source is also measured short. 6. When the re-work is needed for the L/DCR matching network, use an ohmmeter across the C to see if the correct R value is measured before powering the VR up; otherwise, the current imbalance due to improper re-work could damage the power trains. 7. After everything is checked, apply low input voltage (1-5V) with appropriate current limiting (~0.5A). All phases should be switching evenly. 8. Remove the pull-up from EN_PWR pin, using bench power supplies, power up VCC with current limiting (typically ~ 0.25A if 5V drivers included) and slowly increase Input Voltage with current limiting. For typical application, VCC limited to 0.25A, VIN limited to 0.5A should be safe for powering up without no load. High core-loss inductors likely need to increase the input current limiting. All phases should be switching evenly.
Voltage-Regulator (VR) Design Materials
The tolerance band calculation (TOB) worksheets for VR output regulation and IMON have been developed using the Root-SumSquared (RSS) method with 3 sigma distribution point of the related components and parameters. Note that the "Electrical Specifications" table beginning on page 8 specifies no less than 6 sigma distribution point, not suitable for RSS TOB calculation. To support VR design and layout, Intersil also developed a set of worksheets and evaluation boards, as listed in Tables 15 and 16, respectively. Contact Intersil's local office or field support for the latest available information.
TABLE 15. AVAILABLE DESIGN ASSISTANCE MATERIALS ITEM 0 1 2 3 4 5 6 7 8 9 10 DESCRIPTION VR12 Design and Validation VR12 Design Worksheet for Compensation and Component Selection Transient Response Optimization Guidelines VOUT and IMON TOB Calculator SVID and PMBus Communication Tool Resistor Register Calculator Dynamic VID Compensation Calculator VR12 Layout Design Guidelines TCOMP and TM Selection Worksheet Fine Tune OCP and Droop Worksheet Evaluation Board Schematics in OrCAD Format and Layout in Allegro Format
NOTE: For worksheets, please contact Intersil Application support
at www.intersil.com/design/.
TABLE 16. AVAILABLE VR12 EVALUATION BOARDS EVALUATION BOARDS ISL6366/67EVAL1 ISL6366/67EVAL2 ISL6364EVAL1 ISL6363EVAL1 ISL6353EVAL1 # OF # OF INTEGRATED PHASES DRIVERS 6+1 6+1 4+1 4+1 3+0 2+1 2 PACKAGE 7x7 60Ld 7x7 60Ld 6x6 48Ld 7x7 60Ld 5x5 40Ld TARGETED APPLICATIONS High-End Desktop and Server with Discrete Drivers and MOSFETs High-End Desktop and Server with DrMOS Desktop/Memory Desktop/Memory Memory I2C/PMBUS Yes Yes PEAK EFFICIENCY 93%, 1.2V@50A 93.5%, 1.2V@50A 88%, 1.2V@50A 88%, 1.2V@50A 94%, 1.5V@25A PEAK CURRENT 190A +25A 190A +25A 120A +35A 120A +35A 100A
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FN6964.0 January 3, 2011
ISL6366 Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision.
DATE 1/3/11 REVISION FN6964.0 Initial Release. CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL6366 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com
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FN6964.0 January 3, 2011
ISL6366
Package Outline Drawing
L48.6x6B
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 9/09
4X 4.4 6.00 A B 6 PIN 1 INDEX AREA 37 36 44X 0.40 48 1 6 PIN #1 INDEX AREA
6.00
4 .40 0.15
25 (4X) 0.15 24
TOP VIEW
12 13
0.10 M C A B 0.05 M C
48X 0.45 0.10
BOTTOM VIEW
4 48X 0.20
SEE DETAIL "X" MAX 1.00 ( 5. 75 TYP ) ( 4. 40 ) ( 44 X 0 . 40 )
SIDE VIEW
0.10 C BASE PLANE
C
SEATING PLANE 0.08 C
C ( 48X 0 . 20 )
0 . 2 REF
5
( 48X 0 . 65 )
TYPICAL RECOMMENDED LAND PATTERN
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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FN6964.0 January 3, 2011

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